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path: root/src/gallium/drivers/nouveau/codegen
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* nvc0/ir: cache vertex out base so that we don't recompute againIlia Mirkin2015-07-291-8/+15
* nvc0/ir: output base for reading is based on laneidIlia Mirkin2015-07-291-0/+25
* nvc0/ir: trim out barrier sync for non-compute shadersIlia Mirkin2015-07-281-0/+6
* nvc0/ir: fix barrier emissionIlia Mirkin2015-07-281-0/+2
* nvc0/ir: per-patch vars are in a separate address spaceIlia Mirkin2015-07-241-0/+2
* nvc0/ir: kepler can't do indirect shader input/output loads directlyIlia Mirkin2015-07-238-6/+75
* nvc0/ir: tess factors are now sysvals, adapt codegen to expect thatIlia Mirkin2015-07-236-11/+24
* gk110/ir: fake BAR supportIlia Mirkin2015-07-231-0/+12
* nvc0/ir: cleanup private enums that have graduated to galliumIlia Mirkin2015-07-231-5/+0
* nvc0/ir: allow tess eval output loads to be CSE'dIlia Mirkin2015-07-231-0/+2
* nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argumentIlia Mirkin2015-07-231-0/+2
* nvc0/ir: patch vertex count is stored in the upper bitsIlia Mirkin2015-07-231-0/+4
* nvc0/ir: add support for reading outputs in tess control shadersIlia Mirkin2015-07-232-2/+18
* nvc0/ir: set perPatch flag on load/stores to per-patch varyingsIlia Mirkin2015-07-231-2/+6
* nvc0/ir: populate info structure based on new tess propertiesIlia Mirkin2015-07-231-0/+18
* nvc0/ir: mark varyings as per-patch based on semantic nameIlia Mirkin2015-07-231-0/+14
* nvc0: TESSCOORD comes in as a sysval, not an inputIlia Mirkin2015-07-231-2/+0
* nvc0: preliminary tess supportIlia Mirkin2015-07-233-7/+4
* nouveau: use bool instead of booleanSamuel Pitoiset2015-07-213-12/+12
* gm107/ir: fix indirect txq emissionIlia Mirkin2015-07-181-2/+8
* nvc0/ir: don't worry about sampler in txq handlingIlia Mirkin2015-07-181-22/+8
* nvc0/ir: fix txq on indirect samplersIlia Mirkin2015-07-182-2/+56
* nv50/ir: UCMP arguments are float, so make sure modifiers are appliedIlia Mirkin2015-07-031-1/+2
* nv50/ir: don't emit src2 in immediate formIlia Mirkin2015-07-021-2/+2
* nv50/ir: copy joinAt when splitting both before and afterIlia Mirkin2015-07-013-0/+5
* nv50/ir: fix emission of address reg in 3rd sourceIlia Mirkin2015-06-301-2/+6
* nv50/ir: propagate modifier to right arg when const-folding madIlia Mirkin2015-06-261-1/+4
* nvc0/ir: can't have a join on a load with an indirect sourceIlia Mirkin2015-06-171-1/+1
* nvc0/ir: fix collection of first uses for texture barrier insertionIlia Mirkin2015-06-151-5/+11
* nv50/ir: OP_JOIN is a flow instructionJürgen Rühle2015-06-151-1/+1
* nv50/ir: avoid messing up arg1 of PFETCHIlia Mirkin2015-05-231-2/+18
* nvc0/ir: LOAD's can't be used for shader inputsIlia Mirkin2015-05-222-0/+2
* nv50/ir: guess that the constant offset is the starting slot of arrayIlia Mirkin2015-05-221-2/+4
* nvc0/ir: set ftz when sources are floats, not just destinationsIlia Mirkin2015-05-221-3/+2
* nv50/ir: allow OP_SET to merge with OP_SET_AND/etc as well as a negIlia Mirkin2015-05-221-26/+55
* nvc0/ir: optimize set & 1.0 to produce boolean-float setsIlia Mirkin2015-05-222-0/+29
* nvc0/ir: allow iset to produce a boolean floatIlia Mirkin2015-05-223-5/+16
* nvc0/ir: avoid jumping to a sched instructionIlia Mirkin2015-05-223-2/+9
* gallium: remove TGSI_SAT_MINUS_PLUS_ONEMarek Olšák2015-05-201-12/+1
* gk110/ir: switch to gk104-style sched codes rather than all-in-oneIlia Mirkin2015-05-181-9/+9
* nv50/ir: silence compiler warnings about mismatched tagsSamuel Pitoiset2015-05-141-3/+3
* nv50/ir: remove unused private field cycle to SchedDataCalculatorSamuel Pitoiset2015-05-141-1/+0
* nv50/ir: only enable mul saturate on G200+Ilia Mirkin2015-05-091-1/+4
* nv50/ir: only propagate saturate up if some actual folding took placeIlia Mirkin2015-05-081-1/+2
* nv50/ir: add SHL to the list of U32 opcodesIlia Mirkin2015-05-061-0/+1
* nvc0/ir: fix predicated PFETCH for realIlia Mirkin2015-04-302-2/+2
* nv50/ir: fix asFlow() const helper for OP_JOINIlia Mirkin2015-04-291-1/+1
* nvc0/ir: fix predicated PFETCH emissionIlia Mirkin2015-04-292-2/+6
* gk110/ir: fix set with a register dest to not auto-set the abs flagIlia Mirkin2015-04-291-1/+1
* nvc0/ir: flush denorms to zero in non-compute shadersIlia Mirkin2015-04-282-1/+25
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