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path: root/src/gallium/drivers/nouveau/codegen
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* nouveau: Fix a couple of "foo may be used uninitialized' compiler warningsHans de Goede2016-07-021-2/+2
* nouveau: Fix gcc6 / c++11 auto_ptr deprecation compiler warningsHans de Goede2016-07-021-0/+4
* nouveau: Add support for SV_WORK_DIMHans de Goede2016-07-024-0/+5
* nvc0: fix up image support for allowing multiple samplesIlia Mirkin2016-07-012-32/+51
* nv50/ir: print EMIT subops in debug modeSamuel Pitoiset2016-06-291-0/+9
* nv50/ir: print RSQ/RCP subops in debug modeSamuel Pitoiset2016-06-291-0/+10
* nv50/ir: print PIXLD subops in debug modeSamuel Pitoiset2016-06-291-0/+9
* nv50/ir: print SHFL subops in debug modeSamuel Pitoiset2016-06-291-0/+9
* gm107/ir: make sure that flagsDef is set when emitting setcondSamuel Pitoiset2016-06-281-1/+1
* gm107/ir: add missing setcond flags for LOP variantsSamuel Pitoiset2016-06-281-0/+2
* gm107/ir: make use of LOP32I for all immediatesSamuel Pitoiset2016-06-281-1/+1
* gm107/ir: make use of MOV32I for all immediatesSamuel Pitoiset2016-06-271-2/+1
* gm107/ir: make use of IMUL32I for all immediatesSamuel Pitoiset2016-06-261-1/+1
* Remove wrongly repeated words in commentsGiuseppe Bilotta2016-06-231-1/+1
* gk104/ir: fix tex use generation to be more careful about eliding usesIlia Mirkin2016-06-192-12/+27
* nv50/ir: add missing strings for some recent sysvalsSamuel Pitoiset2016-06-181-0/+3
* nv50/ir: make Graph destructor virtualStephan Bergmann2016-06-131-1/+1
* nvc0/ir: clamp the UBO index for compute on KeplerSamuel Pitoiset2016-06-131-1/+9
* nv50: enable indirect addressing of fragment shader inputsIlia Mirkin2016-06-111-0/+1
* gk104/ir: fix conditions for adding a texbarIlia Mirkin2016-06-071-4/+6
* nvc0: add support for VOTE tgsi opcodesIlia Mirkin2016-06-064-21/+75
* nv50/ir: use round toward 0 when converting doubles to integersSamuel Pitoiset2016-06-061-1/+3
* nv50/ir: fix error finding free element in bitset in some situationsIlia Mirkin2016-05-311-0/+6
* nv50/ir: print relevant file's bitset when showing RA infoIlia Mirkin2016-05-311-4/+4
* nvc0/ir: fix spilling predicates to registersIlia Mirkin2016-05-301-0/+4
* nvc0/ir: limit max number of regs based on availability in SMIlia Mirkin2016-05-302-2/+4
* nv50/ir: record number of threads in a compute shaderIlia Mirkin2016-05-305-2/+10
* nv50/ir: Add missing handling of U64/S64 in inlinesPierre Moreau2016-05-301-1/+3
* nvc0/ir: fix emission of predicate spill to registerIlia Mirkin2016-05-301-1/+2
* nv50,nvc0: fix the max_vertices=0 caseIlia Mirkin2016-05-291-0/+2
* gk110/ir: fix unspilling of predicates from registersIlia Mirkin2016-05-281-0/+28
* nvc0/ir: handle a load's reg result not being used for locked variantsIlia Mirkin2016-05-263-11/+45
* nvc0/ir: avoid generating illegal instructions for compute constbuf loadsIlia Mirkin2016-05-261-1/+2
* nvc0/ir: fix indirect access for imagesSamuel Pitoiset2016-05-221-8/+14
* nv50/ir: fix prog info initIlia Mirkin2016-05-221-3/+1
* nvc0/ir: return 0 for gl_TessCoord.z for non-triangles modesIlia Mirkin2016-05-221-0/+4
* nvc0/ir: add a lowering pass for surfaces on FermiSamuel Pitoiset2016-05-212-0/+117
* nvc0/ir: add emission for SULDB and SUSTxSamuel Pitoiset2016-05-211-2/+44
* nvc0/ir: add emission for OP_SULEASamuel Pitoiset2016-05-211-0/+58
* nv50/ir: fix tex constraints for surface coords on FermiSamuel Pitoiset2016-05-211-0/+6
* nv50/ir: use moveSources to condense sourcesIlia Mirkin2016-05-211-6/+1
* nvc0/ir: don't check the format for surface stores on KeplerSamuel Pitoiset2016-05-211-8/+7
* nv50/ir: fix a comment in canDualIssue()Samuel Pitoiset2016-05-211-1/+1
* nv50/ir: fix SUSTx constraints on KeplerSamuel Pitoiset2016-05-211-3/+1
* nv50/ir: treat addresses as localIlia Mirkin2016-05-191-1/+1
* Treewide: Remove Elements() macroJan Vesely2016-05-173-6/+6
* nvc0/ir: fix shared atomic lowering to preserve shared memory locationIlia Mirkin2016-05-171-10/+8
* nvc0/ir: make sure out-of-bounds buffer loads/atomics get a 0 resultIlia Mirkin2016-05-171-1/+26
* nv50/ir: avoid asserts when the state tracker feeds us bogus inputsIlia Mirkin2016-05-151-12/+48
* nvc0/ir: make sure to align the second arg of TXD to 4, as we do for TEXIlia Mirkin2016-05-151-0/+14
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