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path: root/src/gallium/drivers/nouveau/codegen
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* nvc0/ir: Only store viewport in scratch register for GPLyude2017-04-201-0/+1
* nvc0/ir: Implement TGSI_OPCODE_BALLOT and TGSI_OPCODE_READ_*Boyan Ding2017-04-131-0/+31
* nvc0/ir: Implement TGSI_SEMANTIC_SUBGROUP_*Boyan Ding2017-04-131-0/+27
* nvc0/ir: Add SV_LANEMASK_* system values.Boyan Ding2017-04-135-0/+25
* nvc0/ir: Allow 0/1 immediate value as source of OP_VOTEBoyan Ding2017-04-133-11/+60
* gk110/ir: Emit OP_SHFLBoyan Ding2017-04-131-0/+56
* nvc0/ir: Emit OP_SHFLBoyan Ding2017-04-131-0/+53
* nvc0/ir: Properly handle a "split form" of predicate destinationBoyan Ding2017-04-131-2/+13
* gm107/ir: Emit third src 'bound' and optional predicate output of SHFLBoyan Ding2017-04-132-9/+29
* nv50/ir: remove unused swizzle field in ValueRefIlia Mirkin2017-04-091-1/+0
* nv50/ir: Handle TGSI_OPCODE_CLOCKBoyan Ding2017-04-091-0/+7
* gm107/ir: Emit SV_CLOCK system valueBoyan Ding2017-04-091-0/+1
* nvc0/ir: fix overwriting of offset register with interpolateAtOffsetIlia Mirkin2017-04-071-2/+2
* nvc0/ir: fix LSB/BFE/BFI implementationsIlia Mirkin2017-04-071-8/+11
* nv50/ir: also do PostRaLoadPropagation for FMAKarol Herbst2017-03-312-1/+2
* gm107/ir: add LIMM form of madKarol Herbst2017-03-312-11/+26
* gk110/ir: add LIMM form of madKarol Herbst2017-03-312-18/+34
* nv50/ir: implement mad post ra folding for nvc0+Karol Herbst2017-03-311-4/+47
* nv50/ir: restructure and rename postraconstantfolding passKarol Herbst2017-03-311-58/+63
* nvc0/ir: also do ConstantFolding for FMAKarol Herbst2017-03-311-0/+1
* nvc0/ir: disable support for LIMMs on MAD/FMAKarol Herbst2017-03-311-8/+2
* gallium: remove support for predicates from TGSI (v2)Marek Olšák2017-04-011-9/+1
* nv50,nvc0: enable TEX_LZ and TXF_LZIlia Mirkin2017-03-181-2/+15
* nvc0/ir: treat FMA like MAD for operand propagationKarol Herbst2017-03-181-0/+1
* nv50/ir: check for origin insn in findOriginForTestWithZeroPierre Moreau2017-03-091-0/+2
* gallium: remove TGSI_OPCODE_CLAMPMarek Olšák2017-02-181-10/+0
* gm107/ir: fix address offset bitfield for ATOMSIlia Mirkin2017-02-111-1/+1
* nv50/ir: convert an ATOM.EXCH without a destination into a storeIlia Mirkin2017-02-111-0/+5
* nv50/ir: return a register when retrieving thread id sysvalIlia Mirkin2017-02-111-1/+1
* nv50/ir: add missing break after DSSGIlia Mirkin2017-02-111-0/+1
* nvc0/ir: fix ubo max clamp, reset file indexIlia Mirkin2017-02-091-1/+3
* nv50/ir: always return 0 when trying to read thread id along unit dimIlia Mirkin2017-02-094-5/+17
* nvc0/ir: fix robustness guarantees for constbuf loads on kepler+ computeIlia Mirkin2017-02-091-25/+22
* nvc0/ir: make it possible to have the flags def in def0Ilia Mirkin2017-02-095-12/+15
* nvc0/ir: add support for 64-bit shift lowering on SM20/SM30Ilia Mirkin2017-02-091-6/+62
* nvc0/ir: add support for all the new int64 tgsi opcodesIlia Mirkin2017-02-096-5/+302
* nv50/ir: Split 64-bit integer MAD/MUL operationsPierre Moreau2017-02-091-0/+116
* nvc0/ir: add a "high" subop for shifts, emit shf.l/shf.r for 64-bitIlia Mirkin2017-02-093-3/+74
* nvc0/ir: fix SET and SLCT emissionIlia Mirkin2017-02-092-0/+6
* nvc0/ir: add support for emitting partial min/max ops for int64Ilia Mirkin2017-02-094-1/+14
* nouveau: remove explicit __STDC_FORMAT_MACROS defineEmil Velikov2017-01-271-1/+0
* nvc0: add support for MUL_ZERO_WINS propertyIlia Mirkin2017-01-233-8/+24
* nv50/ir: optimize shl + andIlia Mirkin2017-01-161-0/+11
* nvc0: enable FBFETCH with a special slot for color buffer 0Ilia Mirkin2017-01-163-4/+59
* nv50/ir: handle new DDIV op which will be used for double divisionsIlia Mirkin2017-01-161-0/+3
* nvc0/ir: emit FMZ flag when requested on FFMAIlia Mirkin2017-01-151-0/+4
* nvc0/ir: only try to check for zero LOD if we aren't already forcing itIlia Mirkin2017-01-121-1/+1
* nv50/ir: use sched control codes for gm107 builtinsSamuel Pitoiset2017-01-122-40/+40
* nv50/ir: improve instruction pipelining on gm107Samuel Pitoiset2017-01-123-4/+1027
* nv50/ir: do not insert texture barriers on gm107Samuel Pitoiset2017-01-121-1/+2
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