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* nvc0/ir: Properly lower 64-bit shifts when the shift value is >32Pierre Moreau2017-12-041-1/+1
* nouveau/compiler: Allow to omit line numbers when printing instructionsTobias Klausmann2017-11-262-4/+10
* nv50/ir: move LateAlgebraicOpt to the very endIlia Mirkin2017-11-261-1/+1
* nv50/ir: when merging immediates/consts, load directlyIlia Mirkin2017-11-261-1/+21
* nv50/ir: add optimization for modulo by a non-power-of-2 valueIlia Mirkin2017-11-261-0/+15
* nv50/ir: optimize signed integer modulo by pow-of-2Ilia Mirkin2017-11-252-10/+29
* nv50/ir: Store shared memory per block in nv50_ir_prog_infoPierre Moreau2017-11-041-0/+1
* nv50/ir: fix 64-bit integer shiftsIlia Mirkin2017-10-091-1/+3
* nvc0/ir: propagate immediates to CALL input MOVsTobias Klausmann2017-08-311-2/+19
* nv50/ir: properly set sType for TXF ops to U32Ilia Mirkin2017-08-241-0/+3
* gallium: remove TGSI opcode SCSMarek Olšák2017-08-221-14/+0
* gallium: remove TGSI opcode XPDMarek Olšák2017-08-221-27/+0
* gallium: remove TGSI opcode DPHMarek Olšák2017-08-221-8/+0
* gallium: remove TGSI FENCE opcodesMarek Olšák2017-08-221-10/+0
* gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZMarek Olšák2017-08-221-3/+0
* nv50/ir: fix TXQ srcMaskIlia Mirkin2017-08-161-0/+2
* nv50/ir: fix srcMask computation for TG4 and TXFIlia Mirkin2017-08-161-0/+2
* nv50/ir: clean up saturated values immediatelyIlia Mirkin2017-08-121-1/+6
* nvc0/ir: unlink values pre- and post-call to division functionIlia Mirkin2017-08-121-4/+3
* nv50/ir: fix ConstantFolding with saturationKarol Herbst2017-08-092-0/+9
* nv50/ir: disable mul+add to mad for precise instructionsKarol Herbst2017-07-211-2/+3
* nv50/ir/tgsi: handle precise for most ALU instructionsKarol Herbst2017-07-211-0/+2
* nv50/ir: add precise field to InstructionKarol Herbst2017-07-212-0/+3
* nv50/ir: fix threads calculation for non-compute shadersIlia Mirkin2017-07-121-5/+9
* nv50/ir: fix combineLd/St to update existing records as necessaryIlia Mirkin2017-06-261-0/+8
* nv50/ir: adjust overlapping logic to take fileIndex-relative offsetsIlia Mirkin2017-06-261-1/+5
* nv50/ir: VFETCH is also considered a load for MemoryOptIlia Mirkin2017-06-261-1/+1
* nv50/ir: fetch indirect sources BEFORE the op that uses themIlia Mirkin2017-06-261-19/+32
* nv50/ir: Properly fold constants in SPLIT operationPierre Moreau2017-06-251-3/+4
* nvc0: Add support for ARB_post_depth_coverageLyude2017-06-022-0/+4
* nouveau: drop Android 4.4 and earlier supportRob Herring2017-05-252-33/+3
* nvc0/ir: SHLADD's middle source must be an immediateIlia Mirkin2017-05-201-0/+2
* nv50/ir: Report wrong prog types using proper varPierre Moreau2017-05-131-1/+1
* nv50/ir: Replace NV50_PROGRAM_IR_* by PIPE_SHADER_IR_*Pierre Moreau2017-05-072-7/+2
* nv50/ir: Remove unused translation methodsPierre Moreau2017-05-072-10/+3
* nv50/ir: Free target if we failed to create a programPierre Moreau2017-05-071-1/+3
* nv50/ir: Fail if encountering unknown shader typePierre Moreau2017-05-071-2/+2
* gm107/ir: add a missing assertion in emitISCADD()Samuel Pitoiset2017-05-011-0/+2
* nvc0/ir: Only store viewport in scratch register for GPLyude2017-04-201-0/+1
* nvc0/ir: Implement TGSI_OPCODE_BALLOT and TGSI_OPCODE_READ_*Boyan Ding2017-04-131-0/+31
* nvc0/ir: Implement TGSI_SEMANTIC_SUBGROUP_*Boyan Ding2017-04-131-0/+27
* nvc0/ir: Add SV_LANEMASK_* system values.Boyan Ding2017-04-135-0/+25
* nvc0/ir: Allow 0/1 immediate value as source of OP_VOTEBoyan Ding2017-04-133-11/+60
* gk110/ir: Emit OP_SHFLBoyan Ding2017-04-131-0/+56
* nvc0/ir: Emit OP_SHFLBoyan Ding2017-04-131-0/+53
* nvc0/ir: Properly handle a "split form" of predicate destinationBoyan Ding2017-04-131-2/+13
* gm107/ir: Emit third src 'bound' and optional predicate output of SHFLBoyan Ding2017-04-132-9/+29
* nv50/ir: remove unused swizzle field in ValueRefIlia Mirkin2017-04-091-1/+0
* nv50/ir: Handle TGSI_OPCODE_CLOCKBoyan Ding2017-04-091-0/+7
* gm107/ir: Emit SV_CLOCK system valueBoyan Ding2017-04-091-0/+1
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