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path: root/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
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* nv50/ir: remove DUMMY edge typeKarol Herbst2019-10-171-2/+0
* nvc0/ir: fix second tex argument after levelZero optimizationIlia Mirkin2019-02-061-9/+24
* gm107/ir: disable TEXS for tex with derivAll setKarol Herbst2019-01-181-1/+2
* nv50/ir: initialize relDegree staticlyKarol Herbst2018-12-091-7/+16
* nv50/ir/ra: enforce max register requirement, and change spill orderIlia Mirkin2018-11-161-9/+16
* nv50/ir/ra: improve condition for short regs, unify with cond for 16-bitIlia Mirkin2018-11-161-7/+7
* gm107/ir: use scalar tex instructions where possibleKarol Herbst2018-11-061-0/+162
* nv50/ra: add condenseDef overloads for partial condensesKarol Herbst2018-11-061-8/+21
* nv50/ir: only avoid spilling constrained def if a mov is addedKarol Herbst2018-06-231-2/+2
* nv50/ir: make a copy of tex src if it's referenced multiple timesIlia Mirkin2018-04-221-37/+49
* nv50/ir/ra: prefer def == src2 for fma with immediates on nvc0Karol Herbst2018-04-211-10/+29
* nv50/ir: when merging immediates/consts, load directlyIlia Mirkin2017-11-261-1/+21
* nouveau: drop Android 4.4 and earlier supportRob Herring2017-05-251-3/+1
* nv50/ir: also do PostRaLoadPropagation for FMAKarol Herbst2017-03-311-1/+1
* nv50/ir: copy over value's register id when resolving merge of a phiIlia Mirkin2016-10-121-1/+3
* nv50/ra: let simplify return an error and handle thatKarol Herbst2016-10-051-5/+7
* gm107/ra: fix constraints for surface operationsSamuel Pitoiset2016-07-201-2/+23
* nvc0: initial support for GP100 GPUsBen Skeggs2016-07-121-0/+2
* nv50/ir: print relevant file's bitset when showing RA infoIlia Mirkin2016-05-311-4/+4
* nv50/ir: fix tex constraints for surface coords on FermiSamuel Pitoiset2016-05-211-0/+6
* nv50/ir: use moveSources to condense sourcesIlia Mirkin2016-05-211-6/+1
* nv50/ir: fix SUSTx constraints on KeplerSamuel Pitoiset2016-05-211-3/+1
* nvc0/ir: fix constraints for OP_SUSTx on KeplerSamuel Pitoiset2016-04-261-1/+3
* Revert "nv50/ra: `isinf()` is in namespace `std` since C++11."Jose Fonseca2016-04-191-4/+0
* nv50/ra: `isinf()` is in namespace `std` since C++11.Pierre Moreau2016-04-131-0/+4
* nv50/ir: Check for valid insn instead of def sizePierre Moreau2016-03-311-2/+2
* nvc0: initial support for GM20x GPUsBen Skeggs2016-02-161-0/+2
* nv50/ir: fix memory corruption when spilling and redoing RAKarol Herbst2016-01-261-0/+3
* nv50/ir: add short imad supportIlia Mirkin2015-12-121-1/+0
* nv50/ir: prefer to color mad def and src2 with the same colorIlia Mirkin2015-12-081-0/+14
* nv50/ir: reduce degree limit on ops that can't encode large reg destsIlia Mirkin2015-12-081-3/+34
* nv50/ir: only unspill once ahead of a group of instructionsIlia Mirkin2015-12-081-5/+20
* nv50/ir: fix moves to/from flagsIlia Mirkin2015-12-021-0/+4
* nv50/ir: do not call textureMask() for surface opsSamuel Pitoiset2015-12-021-1/+2
* nv50/ir: fix (un)spilling of 3-wide resultsIlia Mirkin2015-11-221-4/+42
* nv50/ir: use C++11 standard std::unordered_map if possibleChih-Wei Huang2015-10-151-3/+17
* nv50/ir: make edge splitting fix up phi node sourcesIlia Mirkin2015-09-101-13/+77
* nv50/ir: support different unordered_set implementationsChih-Wei Huang2015-08-201-3/+2
* nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argumentIlia Mirkin2015-07-231-0/+2
* gm107/ir: fix texture argument orderIlia Mirkin2014-09-251-0/+7
* nv50/ir: avoid deleting pseudo instructions too earlyIlia Mirkin2014-09-251-1/+10
* nv50/ir/util: fix BitSet issuesChristoph Bumiller2014-09-051-0/+4
* nv50/ir: fix phi/union sources when their def has been mergedIlia Mirkin2014-07-241-0/+8
* nv50/ir: fix hard-coded TYPE_U32 sized registerIlia Mirkin2014-07-241-3/+4
* nv50/ir: use unordered_set instead of list to keep track of var usesTobias Klausmann2014-07-081-2/+2
* nv50/ir: make sure that texprep/texquerylod's args get coalescedIlia Mirkin2014-05-181-0/+2
* nvc0: add maxwell (sm50) compiler backendBen Skeggs2014-05-151-0/+33
* nvc0/ir: move sample id to second source arg to fix sampler2DMSIlia Mirkin2014-03-201-1/+1
* nv50/ir/ra: fix SpillCodeInserter::offsetSlot usageChristoph Bumiller2014-02-221-7/+7
* nv50/ir/ra: some register spilling fixesChristoph Bumiller2014-02-091-5/+34
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