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* iris: Bail resource creation upon aux creation errorNanley Chery2019-10-291-16/+17
| | | | | | | | The functions used during aux buffer configuration and creation only return false for exceptional errors. Don't proceed with surface creation in those cases. Reviewed-by: Jordan Justen <[email protected]>
* iris: Drop iris_resource::aux::extra_aux::boNanley Chery2019-10-292-16/+3
| | | | | | | | The primary and secondary aux buffers are always allocated in the same BO. Suggested-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* iris: Implement new way for setting streamout buffers.Plamena Manolova2019-10-292-3/+23
| | | | | | | | | For gen12 we set the streamout buffers using 4 separate commands instead of 3DSTATE_SO_BUFFER. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* loader: default to iris for all future PCI IDsEric Engestrom2019-10-281-0/+1
| | | | | | | | | | The existing "fallback" code didn't actually do anything, so this removes it, and instead we just always fallback to `iris` for future PCI IDs. Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Create resource with aux_usage MCS_CCSSagar Ghuge2019-10-281-1/+2
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Get correct resource aux usage for copySagar Ghuge2019-10-281-0/+1
| | | | | | | | | | Add case for MCS_CCS so that we get the correct aux usage while copy operation. v2: Fix commit subject (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Define MCS_CCS state transitions and usagesSagar Ghuge2019-10-282-5/+10
| | | | | | | | v2: 1) Fix assertion check (Nanley Chery) 2) Correct commit subject (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Initialize CCS to fast clear while using with MCSSagar Ghuge2019-10-281-3/+14
| | | | | | | | | | v2: Explain Bsepc quotes properly (Nanley Chery) v3: 1) Fix comment format (Nanley Chery) 2) Fix typo in comment (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Disallow incomplete resource creationNanley Chery2019-10-281-2/+6
| | | | | | | | If a modifier specifies an aux, it must be created. Fixes: 75a3947af46 ("iris/resource: Fall back to no aux if creation fails") Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Don't leak the resource for unsupported modifierNanley Chery2019-10-281-1/+1
| | | | | | | | Make sure the res struct is free'd before returning. Fixes: 2dce0e94a3d ("iris: Initial commit of a new 'iris' driver for Intel Gen8+ GPUs.") Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Enable HIZ_CCS samplingNanley Chery2019-10-283-8/+24
| | | | | Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Start using blorp_can_hiz_clear_depth()Nanley Chery2019-10-281-1/+7
| | | | | | | | Check that the alignment requirements for HIZ_CCS are satisfied by using this function. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Enable HIZ_CCS in depth buffer instructionsNanley Chery2019-10-282-3/+7
| | | | | Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Define initial HIZ_CCS state and transitionsNanley Chery2019-10-283-13/+20
| | | | | | | Make it match those of HIZ. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Create an unusable secondary aux surfaceNanley Chery2019-10-282-6/+49
| | | | | | | | | | | | The HIZ_CCS and MCS_CCS auxiliary surface modes require that drivers store information about two aux buffers. We choose to represent this as HiZ/MCS being the primary aux surface and the CCS as an secondary/extra aux surface. This representation has the effect of placing most of the code that will have to choose between the two aux surfaces around the aux-map entry points. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Don't guess the aux_usageNanley Chery2019-10-281-96/+72
| | | | | | | | | Instead of guessing an aux_usage, then confirming it if the isl_surf_get_*_surf functions are successful, just call the ISL functions up-front. This will help us to more easily determine if a depth buffer supports HIZ_CCS. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Support HIZ_CCS in isl_surf_get_ccs_surfNanley Chery2019-10-281-1/+1
| | | | | | | Add an extra aux parameter which will be filled out with CCS if the first two isl_surf parameters fit the requirements for HiZ_CCS. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Clear ::has_hiz when disabling auxNanley Chery2019-10-281-0/+1
| | | | | Fixes: 2cddc953cd0 ("iris: some initial HiZ bits") Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Allow for non-Y-tiled aux allocationNanley Chery2019-10-281-1/+2
| | | | | | | | The Gen12 CCS is not Y-tiled. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* iris: Don't assume CCS_E includes CCS_DNanley Chery2019-10-281-2/+3
| | | | | | | | There's no longer a clear-only compression mode of CCS on Gen12+. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* iris: Drop support for I915_FORMAT_MOD_Y_TILED_CCS on TGL+Nanley Chery2019-10-281-1/+1
| | | | | | | The format of the CCS has changed. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* iris: Add support for depth bounds testing.Plamena Manolova2019-10-282-0/+24
| | | | | | | | In gen12 we use the 3DSTATE_DEPTH_BOUNDS instruction to enable depth bounds testing. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Mark aux-map BO as used by all batchesJordan Justen2019-10-281-9/+44
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris/gen12: Write GFX_AUX_TABLE base address registerJordan Justen2019-10-285-0/+42
| | | | | | | | Rework: * Move last_aux_map_state to iris_batch. (Nanley, Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Map each surf to it's aux-surf in the aux-map tablesJordan Justen2019-10-282-0/+36
| | | | | | Rework: Nanley Chery Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris/bufmgr: Initialize aux map context for gen12Jordan Justen2019-10-282-0/+62
| | | | | | | | | Reworks: * free gen_buffer in gen_aux_map_buffer_free. (Rafael) * lock around aux_map_bos accesses. (Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Rework edgeflag handlingKenneth Graunke2019-10-232-7/+28
| | | | | | | | | | We were relying on specific pass ordering in st to avoid setting inputs_read/outputs_written for edge flags. Instead, just assume that it happens and throw out the results we don't want. We should probably revisit this and try and add a vertex element property like I originally wanted so we can avoid having it be associated with the VS altogether.
* intel/perf: move registers to their own headerLionel Landwerlin2019-10-231-0/+1
| | | | | | | Will conflict with the genxml RPSTAT register. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris/resource: Use isl surface alignment during bo allocationJordan Justen2019-10-171-1/+3
| | | | | | | | | Reworks: * Change subject from "iris: Align main surface allocation to 64k on gen12+" * Make use of isl surf alignment. (Nanley) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Let isl decide the supported tiling in more situationsJordan Justen2019-10-171-15/+0
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Suggested-by: Nanley Chery <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* nir: support feeding state to nir_lower_clip_[vg]sErik Faye-Lund2019-10-171-3/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* nir: support lowering clipdist to arraysErik Faye-Lund2019-10-171-3/+5
| | | | | | | | This allows us to make sure clipdist is emitted as a scalar array rather than two vec4s. This matches SPIR-V semantics, and will be useful for Zink. Reviewed-by: Marek Olšák <[email protected]>
* iris: finish aux import on get_paramJames Xiong2019-10-151-1/+5
| | | | | | | | | | | | A buffer and its aux are imported separately, if the aux import is not completed yet when resource_get_param is called, merge the separate aux a.k.a the 2nd image into the main image. Fixes: 246eebba4a8 ("iris: Export and import surfaces with modifiers that have aux data") Signed-off-by: James Xiong <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* iris: Implement the Gen < 9 tessellation quads workaroundKenneth Graunke2019-10-141-0/+3
| | | | | | | | Fixes several CTS tests: - KHR-GL46.tessellation_shader.vertex.vertex_spacing - KHR-GL46.tessellation_shader.tessellation_shader_point_mode.points_verification Fixes: 823609b1a39 ("iris/WIP: add broadwell support")
* gallium: rename PIPE_CAP_MAX_FRAMES_IN_FLIGHT to PIPE_CAP_THROTTLEJames Xiong2019-10-141-1/+1
| | | | | | | | | v2: [ Michel Dänzer ] * Update src/gallium/docs/source/screen.rst accordingly Signed-off-by: James Xiong <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> # v1 Reviewed-by: Marek Olšák <[email protected]> # v1
* gallium: remove PIPE_SHADER_CAP_SCALAR_ISAMarek Olšák2019-10-101-1/+0
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: add a strip parameter to nir_serializeMarek Olšák2019-10-101-10/+3
| | | | | | | so that drivers don't have to call nir_strip manually. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* iris: Disable fast clears when running with INTEL_DEBUG=nofcCaio Marcelo de Oliveira Filho2019-10-091-0/+6
| | | | Reviewed-by: Rafael Antognolli <[email protected]>
* iris: Implement the Broadwell NP Z PMA Stall FixKenneth Graunke2019-10-085-2/+209
| | | | | | | | | This should help avoid stalls in the pixel mask array in certain non-promoted depth cases. It especially helps for Z16, as each bit in the PMA corresponds to two pixels when using Z16, as opposed to the usual one pixel. Improves performance in GFXBench5 TRex by 22% (n=1).
* iris: Properly unreference extra VBOs for draw parametersKenneth Graunke2019-10-081-3/+3
| | | | | | | | | bound_vertex_buffers doesn't include extra draw parameters buffers. Tracking this correctly is kind of complicated, and iris_destroy_state isn't exactly in a hot path, so just loop over all VBO bindings. Fixes: 4122665dd90 (iris: Enable ARB_shader_draw_parameters support) Reported-by: Sergii Romantsov <[email protected]>
* iris: Update comment about 3-component formats and buffer texturesKenneth Graunke2019-10-071-5/+7
| | | | | You can't render to PIPE_BUFFER so there's no reason to prefer RGBX. PBO upload would like to use proper RGB textures as source data.
* iris: Allow packed RGB pbo uploadsChris Wilson2019-10-071-2/+2
| | | | | | | | Hitting any fallback path on Broxton as we require clflushing the whole buffer even for an upload of a subtexture. However, since gallium provides a pbo upload path, allow it to sample packed RGB if supported. Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: add PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE to skip util_range lockMarek Olšák2019-10-074-9/+9
| | | | | | | | | u_upload_mgr sets it, so that util_range_add can skip the lock. The time spent in tc_transfer_flush_region decreases from 0.8% to 0.2% in torcs on radeonsi. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Drop vtbl usage for some load_register callsKenneth Graunke2019-10-071-5/+4
| | | | We can just call the actual functions directly.
* iris/state: Move reg/mem load/store functions earlier in fileJordan Justen2019-10-071-124/+122
| | | | Signed-off-by: Jordan Justen <[email protected]>
* meson: drop duplicate inc_nir from libirisEric Engestrom2019-10-071-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: add missing idep_nir_headers in iris_gen_libsEric Engestrom2019-10-071-2/+2
| | | | | | Fixes: 4929f020c37eac5b07f9 ("iris: better SBE") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* iris: Drop bonus parameters from iris_init_*_context()Kenneth Graunke2019-10-073-27/+10
| | | | Nothing uses vtbl or dbg, and screen is available from the batch.
* Revert "iris: Hack up a SKL/Gen9LP PS push constant fifo depth workaround"Kenneth Graunke2019-10-071-23/+0
| | | | | | | This reverts commit 4f857423b3c095516e553b976b41969c2b9721fa. It caused GPU hangs on all affected platforms, in e.g. Piglit bin/stencil-twoside -auto -fbo.
* iris: Hack up a SKL/Gen9LP PS push constant fifo depth workaroundKenneth Graunke2019-10-051-0/+23
| | | | | | | | | | | This is a port of Nanley's 904c2a617d86944fbdc2c955f327aacd0b3df318 from i965 to iris. One concern is that iris uses larger batches, and also emits far fewer commands, so we may come closer to the 500 limit within a batch, and could need to supplement this with actual counting. Manhattan 3.0 had 239 3DSTATE_CONSTANT_PS packets in a batch, Unigine Valley had 155. So it seems like we're still in the realm of safety.
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