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* iris: move iris_vtable to iris_screenMike Blumenkrantz2020-04-2918-186/+200
| | | | | | | | | instead of inlining this into every context, now a struct is used in the screen struct to reduce memory usage and simplify a couple of the methods Closes: https://gitlab.freedesktop.org/kwg/mesa/-/issues/6 Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4376>
* iris/bufmgr: Check if iris_bo_gem_mmap failedDanylo Piliaiev2020-04-291-0/+8
| | | | | | | | | | | After refactoring of iris_bo_map_cpu and iris_bo_map_wc - immediate return of NULL on failure to mmap a buffer was lost. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2855 Fixes: 5bc3f52dd8c2b5acaae959ccae2e1fb7c769bb22 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4786>
* iris: Fix downcast of bound_vertex_buffers from uint64_t to intKenneth Graunke2020-04-291-1/+1
| | | | | | | | | | This is the wrong data type, the original field - and the values we're adding in - are both 64-bit unsigned. Keep the original data type. Thanks to Dave Airlie for finding this while reading the code. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4802>
* iris: fail screen creation when kernel support is not thereLionel Landwerlin2020-04-221-5/+19
| | | | | | | | | | v2: Bump check to I915_PARAM_HAS_CONTEXT_ISOLATION (v4.16) (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2803 Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4643>
* replace imports memory functions with utils memory functionsDylan Baker2020-04-211-0/+1
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
* iris/bufmgr: Add support for MMAP_OFFSET ioctl.Rafael Antognolli2020-04-201-1/+51
| | | | | | | | | | | | | Use the new DRM_IOCTL_I915_GEM_MMAP_OFFSET ioctl when available. [[email protected]: iris port] Signed-off-by: Jordan Justen <[email protected]> v2: Update getparam check (Ken). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
* iris/bufmgr: Factor out GEM_MMAP ioctl from mmap_cpu and mmap_wc.Rafael Antognolli2020-04-201-30/+31
| | | | | | | | | | | | | | | We want to add a new ioctl for mmap'ing buffers, so let's avoid duplicating that code on both functions by extracting it from them first. [[email protected]: iris port] Signed-off-by: Jordan Justen <[email protected]> v2: Rename helper function names (Ken). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1675>
* iris: Enable EXT_depth_bounds_test extension.Rafael Antognolli2020-04-161-0/+2
| | | | | | | | | | | | It was implemented in 1df871f8ff753dd234def380ea0e20d7e81cad9e, but to really enable it we need to enable PIPE_CAP_DEPTH_BOUNDS_TEST. v2: Add release notes (Ian). Suggested-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4540>
* iris: make BATCH_SZ smaller by BATCH_RESERVED bytesPaulo Zanoni2020-04-152-7/+7
| | | | | | | | | | | | | Iris allocates gem buffers using buckets of allocation sizes that are page aligned. We always ask for batch buffers of size BATCH_SZ + BATCH_RESERVED, which is not page aligned: we ask for 65552 bytes, which ends up in the bucket of size 81920, resulting in 20% unused space. Adjust things so there is no waste of space: BATCH_SZ + BATCH_RESERVED is now 65536. Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4561>
* iris: remove useless bo->gtt_offset assignmentPaulo Zanoni2020-04-151-1/+0
| | | | | | | | | We assign a real value a few lines below, and none of the lines in between rely on the zeroed bo->gtt_offset value. Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4561>
* iris: remove unnecessary forward declarationPaulo Zanoni2020-04-151-4/+0
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4561>
* iris: remove hole from struct iris_boPaulo Zanoni2020-04-151-12/+12
| | | | | | | | | | | | | | | | | This decreases the size of the struct on a 64bit machine from 144 to 136. While that's not a lot, this is one of the structs that we're allocating all the time. For a full Aztec run on BDW we allocate this struct 3273 times, and we can have up to 3259 of them live at the same time. So we end up saving just a little over 6 pages for this benchmark. Spotted this while trying to add another bool for an unrelated feature. Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4561>
* iris: drop cache coherent cpu mapping for external BOLionel Landwerlin2020-04-153-1/+19
| | | | | | | | | | | | | | | | | | We have to assume any external buffer could be used by the display HW. In the case that buffer is also CPU mapped, we want to assume no cache coherency as it is only available between GT & CPU, not display. Many thanks to Michel Dänzer for the hint! v2: Move cache coherent drop to bufmgr (Chris) v3: Also make BO external if created with PIPE_BIND_SHARED (Eric) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2552 Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4533>
* iris: make resources take a ref on the screen objectLionel Landwerlin2020-04-113-6/+37
| | | | | | | | | | | | | Because St creates resources from a screen and attach them onto another we need to ensure the resources associated to a screen & bufmgr stay around until we don't need them anymore. Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1373 Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
* iris: share buffer managers accross screensLionel Landwerlin2020-04-114-19/+101
| | | | | | | | | | | | | | | | | | | | St happilly uses pipe_resources created with one screen with other screens. Unfortunately our resources have a single identifier that related to a given screen and its associated DRM file descriptor. To workaround this, let's share the buffer manager between screens for a given DRM device. That way handles are always valid. v2: Don't forget to close the fd that bufmgr now owns Take a copy of the fd to ensure it stays alive even if the dri layer closes it Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1373 Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
* iris: properly free resources on BO allocation failureLionel Landwerlin2020-04-111-2/+2
| | | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
* iris: Stop using cs_prog_data->threadsCaio Marcelo de Oliveira Filho2020-04-093-8/+12
| | | | | | | | | | This is a preparation for dropping this field since this value is expected to be calculated by the drivers now for variable group size case. And also the field would get in the way of brw_compile_cs producing multiple SIMD variants (like FS). Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>
* intel/compiler: Replace cs_prog_data->push.total with a helperCaio Marcelo de Oliveira Filho2020-04-092-5/+6
| | | | | | | | | | | | | | | The push.total field had three values but only one was directly used (size). Replace it with a helper function that explicitly takes the cs_prog_data and the number of threads -- and use that in the drivers. This is a preparation for ARB_compute_variable_group_size where the number of threads (hence the total size for push constants) is not defined at compile time (not cs_prog_data->threads). Reviewed-by: Paulo Zanoni <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>
* intel/fs: Allow multiple slots for positionCaio Marcelo de Oliveira Filho2020-04-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | Change brw_compute_vue_map() to also take the number of pos slots. If more than one slot is used, the VARYING_SLOT_POS is treated as an array. When using Primitive Replication, instead of a single position, the VUE must contain an array of positions. Padding might be necessary (after clip distance) to ensure rest of attributes start aligned. v2: Add note about array in the commit message and assert that pos_slots >= 1 to make clear 0 is invalid. (Jason) Move padding to be after the clip distance. v3: Apply the correct offset when gathering the sources from outputs. Reviewed-by: Jason Ekstrand <[email protected]> [v2] Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2313>
* iris: Set alignments on cbuf0 and constant readsJason Ekstrand2020-04-031-0/+4
| | | | | Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
* meson: inline `inc_common`Eric Engestrom2020-03-281-1/+1
| | | | | | | | | Let's make it clear what includes are being added everywhere, so that they can be cleaned up. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
* intel/perf: break GL query stuff awayLionel Landwerlin2020-03-274-5/+1
| | | | | | | | | | | | | | This stuff is somewhat specific to the GL extension & drivers. On Vulkan we won't use this, it also made a rather large file. v2: Fix Android build (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Tapani Pälli <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Mark Janes <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
* iris: Set patch count threshold in 3DSTATE_HSSagar Ghuge2020-03-231-0/+7
| | | | | | | | | | Lets specifiy maximum number of patches that will be accumulated before a thread is dispatched. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
* intel/iris: Always initialize CCS to 0Jason Ekstrand2020-03-191-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we were initializing the CCS to 0xFF for MCS+CCS due to a misunderstanding of the following lines in the bspec: The following are the general SW requirements for MCS buffer clear functionality: ... - If Software wants to enable Color Compression without Fast clear, Software needs to initialize MCS with zeros. - Lossless compression and CCS initialized to all F (using HW Fast Clear or SW direct Clear) on the same surface is not supported. The first line does not refer to the CCS as the comment author supposed but refers to the MCS as the comment says. It means that if you want to use MCS compression without a fast-clear, you should initialize the MCS to 0x00. This is because the value 0x00 in the MCS means "all data is in plane 0" which is a perfectly valid non-fast-clear initialization. It's also the value the MCS should be in if you do a RECTLIST slow-clear where the primitive fully covers each pixel such that the same value is written to all samples. The second line in the above quote seems to imply that CCS fast-clear is incompatible with MCS fast-clear. In particular, MCS+CCS fast-clear uses a 0xff value in the MCS (like on Gen7-11) and leaves the CCS in either the compressed or the pass-through state. Therefore, we should initialize the CCS to 0x00 even for MCS+CCS surfaces. Reviewed-by: Sagar Ghuge<[email protected]> Reviewed-by: Nanley Chery <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
* intel/blorp: Add support for swizzling fast-clear colorsJason Ekstrand2020-03-181-0/+1
| | | | | | Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
* intel/blorp: Plumb the stage through blorp upload_shaderCaio Marcelo de Oliveira Filho2020-03-172-2/+2
| | | | | | | | | | Vulkan uses that for its own upload function -- even though for BLORP it doesn't really currently care. Neither Iris and i965 makes use of it at the moment. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170>
* iris: allow compression conditionally for images on gen12Tapani Pälli2020-03-161-0/+18
| | | | | | | | | | | | | | With this change, amount of resolves happening with deqp-gles31 (--deqp-case=*load_store*) drops ~50%. v2: use iris_image_view_get_format to get the format, get devinfo from context instead of passing it (Nanley) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: determine aux usage during predraw and state setupTapani Pälli2020-03-162-8/+18
| | | | | | | | | | | | | | | Patch changes surface state setup to alloc/fill states for all possible usages for image resource on gen12. Also predraw and binding table population is changed to determine correct aux usage with the new iris_image_view_aux_usage. v2: alloc always all states independent on current image aux state on gen >= 12 , code cleanups (Nanley) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: move existing image format fallback as a helper functionTapani Pälli2020-03-163-22/+32
| | | | | | | | | | | | Patch adds a helper function for determining image format and changes iris_set_shader_images to use it. v2: pass iris_context instead of pipe one, rename function, code cleanup (Nanley) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: provide dummy iris_image_view_aux_usageTapani Pälli2020-03-162-0/+13
| | | | | | | | | | | | | Similar to iris_resource_texture_aux_usage this function will determine proper aux_usage for image, now it will default to ISL_AUX_USAGE_NONE. v2: drop gen_device_info parameter, rename function (Nanley) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* intel/compiler: detect if atomic load store operations are usedTapani Pälli2020-03-162-1/+5
| | | | | | | | | Patch adds a new arg and modifies existing calls from i965, anv pass NULL but iris stores this information for later use. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: use the images_used mask in resolve passTapani Pälli2020-03-161-3/+3
| | | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: Use ISL_AUX_USAGE_STC_CCS for stencil CCSJason Ekstrand2020-03-123-4/+17
| | | | | Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* iris: Use ISL_AUX_USAGE_HIZ_CCS_WT to indicate write-through HiZJason Ekstrand2020-03-123-10/+22
| | | | | | | | | | | | | Previously, we always set the aux_usage to ISL_AUX_USAGE_HIZ_CCS and let ISL choose write-through based on isl_surf_supports_hiz_ccs_wt. This commit makes us choose explicitly at surface creation time whether to use HIZ_CCS or HIZ_CCS_WT based on the same set of conditions. This is more explicit and should be more robust as it lets us choose WT mode in one place rather than trusting isl_surf_supports_hiz_ccs_wt to return the same thing every time. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* iris: toggle on PIPE_CAP_MIXED_COLOR_DEPTH_BITSTapani Pälli2020-03-121-0/+1
| | | | | | | | | | | This enables additional EGL configs where we have depth/stencil buffer with different number of bits per pixel than color buffer has. This enables some Android games to work that require such config. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4127> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4127>
* iris: Move down iris_emit_sbe_swiz in profiles.Mathias Fröhlich2020-03-101-1/+2
| | | | | | | | | Harvest the information gathered in the previous patch inside of iris. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
* iris: Don't skip fast depth clears if the color changedJason Ekstrand2020-03-061-1/+5
| | | | | | | | | | | | | | | | | We depend on BLORP to convert the clear color and write it into the clear color buffer for us. However, we weren't bothering to call blorp in the case where the state is ISL_AUX_STATE_CLEAR. This leads to the clear color not getting properly updated if we have back-to-back clears with different clear colors. Technically, we could go out of our way to set the clear color directly from iris in this case but this is a case we're unlikely to see in the wild so let's not bother. This matches what we already do for color surfaces. Cc: [email protected] Reported-by: Mark Janes <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4073> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4073>
* iris: Enable HiZ and stencil CCS for blorp blit destinationsJason Ekstrand2020-03-051-36/+25
| | | | | | | | | Now that blorp blits write to depth and stencil as depth and stencil, we can leave HiZ and stencil CCS enabled for blorp blit destinations. Reviewed-by: Nanley Chery <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
* iris: Enable CCS for copies from HiZ+CCS depth buffersJason Ekstrand2020-03-051-8/+12
| | | | | | | | | Ever since b274469daae, BLORP is able to sample from whatever the sampler supports. In c0c899cf7892, we added HiZ support for copies from HiZ compressed depth buffers but forgot HiZ+CCS. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
* iris: Allow HiZ on blit sourcesJason Ekstrand2020-03-051-1/+1
| | | | | | | | | | Ever since 95cc5438ebf, BLORP has been able to read from HiZ-compressed depth buffers as long as the sampler supports HiZ. This just makes iris stop doing the unneeded resolve. Closes: #2583 Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
* intel/gen12+: Disable mid thread preemption.Rafael Antognolli2020-03-031-0/+12
| | | | | | | | | | | | | Fixes a GPU hang in Car Chase. Cc: [email protected] v2: Add comment explaining why (Jason). Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035>
* intel/isl: Implement D16_UNORM workarounds.Rafael Antognolli2020-03-031-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | GEN:BUG:14010455700 (lineage 1808121037): "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501. GEN:BUG:1806527549: "Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM." This one could fix a GPU hang in some workloads. v2: Implement WA in isl and add another similar WA (Jason). v3: Add flushes before changing chicken registers (Jason) v4: Depth flush and stall + end of pipe sync when changing registers (Jason). Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
* intel: fix the gen 12 compute shader scratch IDsPaulo Zanoni2020-03-031-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | This is the same idea as "intel: fix the gen 11 compute shader scratch IDs". The number of EUs on TGL is not the same as ICL, but the MEDIA_VFE_STATE restrictions stay the same, so adapt the code to it. Also, consider the base configuration instead of what we read from the Kernel. According to Mark, this fixes the following piglit tests on TGL: piglit.spec.arb_compute_shader.execution.shared-atomicmax-uint.tglm64 piglit.spec.arb_compute_shader.execution.shared-atomicmax-int.tglm64 piglit.spec.intel_shader_atomic_float_minmax.execution.shared-atomicmax-float.tglm64 v2: s/ICL+/Gen11+/ (Jason). Cc: [email protected] Tested-by: Mark Janes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
* intel: fix the gen 11 compute shader scratch IDsPaulo Zanoni2020-03-031-1/+6
| | | | | | | | | | | | | | | | | | | Scratch space allocation is based on the number of threads in the base configuration, and we only have one base configuration for ICL, with 8 subslices. This fixes an issue with Aztec on Vulkan in a machine with a configuration that's not the base. The issue looks like a regression from b9e93db20896, but it seems things are broken since forever, just not easily reproducible. v2: Reimplement it using the subslices variable. Don't touch TGL. Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
* iris: Wait for the GPU to be idle before invalidating the aux table.Rafael Antognolli2020-03-021-0/+12
| | | | | | | | | An end of pipe sync seems to satisfy this restriction. It takes care of GPU hangs seen in dEQP-GLES31.functional.copy_image.* tests. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
* iris: Split aux map initialization from invalidation.Rafael Antognolli2020-03-023-9/+34
| | | | | | | | We can write the aux map address only once during the batch initialization, and then only invalidate it once we modify it. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
* iris: Apply the flushes when switching pipelines.Rafael Antognolli2020-02-261-12/+4
| | | | | | | | | | | | | | | | | | | | | | Even though the workaround description says: "all the listed commands are non-pipelined and hence flush caused due to pipeline mode change must not cause performance issues..." My understanding is that we still need to have the flushes. Also, the flushes are required not only to stall the pipeline, but also to clear caches, so I don't think they can simply be discarded. Additionally, while doing some testing that increased the number of surface STATE_BASE_ADDRESS emitted, I got a lot more GPU hangs. Adding these flushes fixes those hangs. Fixes: b8fbb39a (iris: Implement Gen12 workaround for non pipelined state) Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3908> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3908>
* iris: Use isl_aux_state_transition_write()Nanley Chery2020-02-241-182/+13
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
* iris: Use ISL's access preparation functionsNanley Chery2020-02-241-256/+34
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
* iris: Use isl_aux_usage_has_fast_clear()Nanley Chery2020-02-243-5/+5
| | | | | | | Make sure fast-clears aren't attempted or allowed for ISL_AUX_USAGE_MC. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-11 22:20:34 +0000