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* iris: Don't mutate box in transfer map codeKenneth Graunke2019-03-131-37/+28
| | | | | | | Not mutating the boxes is arguably cleaner. Split from a patch by Chris Wilson but reworked to use a pointer to the original box rather than making a copy at all.
* iris: Enable auxiliary buffer support againRafael Antognolli2019-03-131-3/+0
| | | | | | | Now that we are properly resolving buffers before giving them to the window system, let's enable aux support again. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Convert RGBX to RGBA always.Rafael Antognolli2019-03-131-14/+27
| | | | | | | | | | | In i965, we disable the use of RGBX formats, so the higher layers of Mesa choose the equivalent RGBA format, and swizzle the alpha channel to 1.0. However, Gallium won't do that. We need to explicitly convert it to RGBA. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Add resolve on iris_flush_resource.Rafael Antognolli2019-03-131-19/+19
| | | | | | | | | | | | | | The flush_resource hook is supposedly called when the resource content needs to be made visible to external (okay, that's pretty vague). For instance, it gets called before a surface gets handled to the window system. So we need to resolve it if it's not resolved yet. v2 (Ken): - Check mod_info in iris_flush_resource instead of ISL_AUX_USAGE_NONE - Drop my old broken resolve code from iris_resource_get_handle() now that Rafael's got it hooked up in the right place. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Use streaming loads to read from tiled surfacesChris Wilson2019-03-132-2/+5
| | | | | | | | | | | Always use the streaming load (since we know we have Broadwell+, all of our target CPU support sse41) for reading back form the tiled surface for mapping the resource. This means we hit the fast WC handling paths on Atoms (without LLC), and for big Core (with LLC) using the streaming load is no less efficient as we do not require the tiled buffer to be pulled into the CPU cache. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Use coherent allocation for PIPE_RESOURCE_STAGINGChris Wilson2019-03-133-1/+24
| | | | | | | | | On !llc machines (Atoms), reading from a linear buffers is slow and so copying from one resource into the linear staging buffer is still slow. However, we can tell the GPU to snoop the CPU cache when reading from and writing to the staging buffer eliminating the slow uncached reads. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Use PIPE_BUFFER_STAGING for the query objectsChris Wilson2019-03-131-1/+1
| | | | | | We prefer fast CPU access to read back the query results. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Flag fewer dirty bits in BLORPSagar Ghuge2019-03-111-3/+27
| | | | | | | | | v2: 1) Skip flagging IRIS_DIRTY_DEPTH_BUFFER if BLORP_BATCH_NO_EMIT_DEPTH_STENCIL is set (Kenneth Graunke) 2) Add missing flags (Kenneth Graunke) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Fix write enable in pinning of depth/stencil resourcesKenneth Graunke2019-03-111-12/+14
| | | | | | | | | | | | | | We may bind new Z/S buffers (which come via the framebuffer CSO, triggering IRIS_DIRTY_DEPTH_BUFFER), but with writes disabled. The next draw may enable Z or S writes (which come via the ZSA CSO, triggering IRIS_DIRTY_WM_DEPTH_STENCIL), which requires us to update our pin to have the write flag. So, update pinning if either dirty flag changes. To clarify, pass cso_zsa to the pinning function rather than pulling the random values out of ice->state, which unfortunately have to exist for the resolve code since iris_depth_stencil_alpha_state only exists in iris_state.c.
* iris: Refactor depth/stencil buffer pinning into a helper.Kenneth Graunke2019-03-111-37/+28
| | | | | | | This avoids the code duplication that caused me to put things in the wrong place in the previous commit. One used to have extra flushes, but we moved those out so now these are identical and can be easily shared.
* iris: Move depth/stencil flushes so they actually do somethingKenneth Graunke2019-03-112-4/+5
| | | | | | | | | | | | | | Commit d6dd57d43cd (iris: Add missing depth cache flushes) added the depth/stencil flushes to the wrong place. I meant to add them to the iris_upload_dirty_render_state code that emits the packets, but I accidentally added them to the nearly identical looking code in iris_restore_render_saved_bos. This meant we missed the actual flushing at draw time, but instead did pointless flushing on the first draw in a batch where things are already flushed anyway. This commit moves them to iris_resolve.c, next to the depth prepares, similar to what we do for color buffers. i965 does them elsewhere, but I'm not sure why - this seems like the most consistent place.
* iris: Fix TES gl_PatchVerticesIn handling.Kenneth Graunke2019-03-112-3/+11
| | | | | | | | | | | | | | | | 1. If we switch the TCS for one with a different number of output vertices, then the TES's gl_PatchVerticesIn value will change. We need to re-upload in this case. For now, re-emit constants whenever the TCS/TES are swapped out. 2. If there is no TCS, then we can't grab gl_PatchVerticesIn from the TCS info. Since it's a passthrough, we can just use the primitive's patch count (like the TCS gl_PatchVerticesIn does). Fixes KHR-GL45.tessellation_shader.single.max_patch_vertices and KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: Rework default tessellation level uploadsKenneth Graunke2019-03-112-39/+33
| | | | | | | | | | | Now that we've added a system value uploading mechanism, we may as well reuse the same system for default tessellation levels. This simplifies the state upload code a bit. Also fixes: KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_tessLevel Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: Face should be a system value.Timur Kristóf2019-03-111-0/+1
| | | | | | | | | | | | This patch adds PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL which despite its name is not a TGSI-specific capability, just lets the state tracker know that it should generate a system value for FACE. This is needed if we want to run tgsi_to_nir on iris. Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Fix backface stencil write conditionKenneth Graunke2019-03-101-1/+1
| | | | A bit too much search and replace here.
* iris: Use copy_region and staging resources to avoid transfer stallsKenneth Graunke2019-03-084-14/+161
| | | | | | | | | | | | This is similar to intel_miptree_map_blit and intel_buffer_object.c's temporary blits in i965. Improves performance of DiRT Rally by 20-25% by eliminating stalls. Breaks piglit's spec/arb_shader_image_load_store/host-mem-barrier, by using the GPU to do uploads, exposing a st/mesa issue where it doesn't give us memory_barrier() calls. This is a pre-existing issue and will be fixed by a later patch (currently out for review).
* iris: Track last VS URB entry sizeSagar Ghuge2019-03-083-0/+11
| | | | | | | | | | | | Return immediately if last VS URB entry size is good enough for BLORP operation v2: Fix comments (Caio) Signed-off-by: Sagar Ghuge <[email protected]> Suggested-by: Kenneth Graunke<[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Refactor code to share 3DSTATE_URB_* packetSagar Ghuge2019-03-083-59/+60
| | | | | | | | | | v2: 1) Set IRIS_DIRTY_URB bit (Caio) 2) Get rid of unnecessary function (Caio) Signed-off-by: Sagar Ghuge <[email protected]> Suggested-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Wire up EGL_IMG_context_priorityChris Wilson2019-03-074-3/+19
| | | | | | | | | Add the missing PIPE_CAP_CONTEXT_PRIORITY_MASK and parsing of the context construction flags. Testcase: piglit/egl-context-priority Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Export a copy_region helper that doesn't flushKenneth Graunke2019-03-072-16/+48
| | | | | | I'll want to use this for transfer maps, which already do their own flushing. This lets us avoid a double flush, and also gives us more control over the batch which is selected.
* iris: Spruce up "are we using this engine?" checks for flushingKenneth Graunke2019-03-072-12/+12
| | | | | | | | | | | | | | We were using batch->contains_draw as a proxy for "are we even using this engine?" That isn't quite right, because it only counts regular draws. BLORP operations may have also rendered to a resource, which needs to trigger flushing. To check for this, we also see if the render and sometimes depth caches are non-empty. We can also drop the "but there might already be stale data in the cache even if we haven't emitted any commands yet" concern in the comments. The kernel flushes caches between batches. This may not be great but it's at least better than what was there.
* iris: Drop PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLYKenneth Graunke2019-03-071-1/+0
| | | | | | | | | | | This cap is mainly for working around a r600 texture swizzle issue, but it also controls whether ARB_texture_buffer_object (with legacy formats) is enabled. I suspect the missing I/L/A/LA faking is why I had it set in the first place. Thanks to Ilia for pointing out that I shouldn't be setting this. Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Properly support alpha and luminance-alpha formatsKenneth Graunke2019-03-074-85/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For texturing, we map alpha formats to the corresponding red format, as many alpha formats are outright missing, and red is more efficient when sampling anyway. When rendering to A8_UNORM, we use that format directly, so the image gets the shader output's .a/.w channel, rather than the .r/.x channel. All other A* formats are non-renderable, so we can't do much and just mark them as unsupported for rendering. Fortunately, GL only requires rendering to A8_UNORM, so that works out. According to Andre Heider and Timur Kristóf, this fixes font rendering in Witcher 1 (via nine). Andre also reported that it fixes Unigine Heaven (presumably via nine). v2: Use the same swizzle for both sampler views and "render targets". BLORP expects the read swizzle, and will take the inverse when setting up the destination swizzle (and actually applying it in the shaders). We ignore the format swizzle when setting up normal rendering SURFACE_STATEs, which is necessary because it would be an illegal shader channel select combination. Thanks to Jason Ekstrand for pointing out that BLORP took an inverse swizzle. Tested-by: Timur Kristóf <[email protected]> Tested-by: Andre Heider <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Defer uploading sampler state tables until draw timeKenneth Graunke2019-03-073-20/+44
| | | | | | | | | | | | | | | | | | | | | | | | | Gallium might call us multiple times to bind subsets of the samplers, at which point we'd recreate the table a bunch of times. It doesn't really buy us anything to do it here - even if we defer to draw time, the dirty tracking ensures we'll only do it on the first draw after a bind_sampler_states() call. We now use the number of samplers specified by the shader instead of the binding count. If this number changes, we flag sampler state as dirty so we re-upload a table with the right number of entries. This also fixes a bug where ice->state.need_border_colors was never unset, so once something needed border colors, the pool would always be pinned in all future batches. v2: Explicitly flag sampler states as dirty, rather than assuming that bind_sampler_states() will be called if the program texture count changes. While this may be true for st/mesa, it isn't the case for Gallium HUD. Tested-by: Timur Kristóf <[email protected]> Tested-by: Andre Heider <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Plumb through ISL_SWIZZLE_IDENTITY in buffer surface emittersKenneth Graunke2019-03-071-6/+8
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Add a swizzle parameter to isl_buffer_fill_state()Kenneth Graunke2019-03-071-0/+3
| | | | | | | This is necessary for legacy texture buffer object formats, where we'll need to use a swizzle to fake e.g. luminance. Reviewed-by: Jason Ekstrand <[email protected]>
* iris: fix decode_get_bo callbackLionel Landwerlin2019-03-071-1/+3
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: acb50d6b1ff1b7 ("intel/decoders: handle decoding MI_BBS from ring") Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: fix decoder callLionel Landwerlin2019-03-071-1/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: acb50d6b1ff1b7 ("intel/decoders: handle decoding MI_BBS from ring")
* iris: add support for tgsi_to_nirAndre Heider2019-03-071-3/+8
| | | | | | | | | | | The Gallium Nine state tracker now works on iris. Also tested with GALLIUM_HUD and Star Wars: Knights of the Old Republic on WINE (GL_ATI_fragment_shader). Signed-off-by: Andre Heider <[email protected]> Reviewed-by: Timur Kristóf <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Fix MOCS for blits and clearsKenneth Graunke2019-03-065-20/+27
| | | | I915_MOCS_CACHED is the wrong value. Expose mocs() and use that.
* iris: setup EdgeFlag Vertex Element when needed.Jose Maria Casanova Crespo2019-03-063-15/+86
| | | | | | | | | | | | | | | | If Vertex Shader uses EdgeFlag the hardware request that it is setup as the last VERTEX_ELEMENT_STATE. If SGVS are add at draw time we need to also reconfigure the last 3DSTATE_VF_INSTANCING so its VertexElementIndex points to the new Vertex Element that contains the EdgeFlag. So if draw parameters or edgeflag are not used the CSO generated at iris_create_vertex_element is sent directly in the batches. But if edge flag is used we adjust last VERTEX_ELEMENT_STATE and last 3DSTATE_VF_INSTANCING using their alternative edge flag version we generate at iris_create_vertex_element and store at the CSO. Reviewed-by: Kenneth Graunke <[email protected]>
* nir/lower_doubles: Inline functions directly in lower_doublesJason Ekstrand2019-03-061-1/+1
| | | | | | | | | | | | Instead of trusting the caller to already have created a softfp64 function shader and added all its functions to our shader, we simply take the softfp64 shader as an argument and do the function inlining ouselves. This means that there's no more nasty functions lying around that the caller needs to worry about cleaning up. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: add libmesa_iris_gen8 library to the buildTapani Pälli2019-02-271-0/+21
| | | | | | | Patch fixes iris build on Android. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* iris: Enable ARB_shader_draw_parameters supportJose Maria Casanova Crespo2019-02-265-4/+212
| | | | | | | | | | | | | | | | | | Additional VERTEX_ELEMENT_STATE are used to store basevertex and baseinstance and drawid updating the DWordLength of the 3DSTATE_VERTEX_ELEMENTS command. This passes all piglit tests for spec.*draw_parameters.* tests and VK-GL-CTS KHR-GL45.shader_draw_parameters_tests.* tests. Now we only mark a dirty_update when parameters are changed or when we have an indirect draw. We enable PIPE_CAP_DRAW_PARAMETERS on Iris. There is no edge flag support in the Vertex Elements setup. Reviewed-by: Kenneth Graunke <[email protected]>
* meson/iris: Use current coding styleDylan Baker2019-02-251-7/+10
| | | | | | Just a few minor style things. Reviewed-by: Jordan Justen <[email protected]>
* iris: Properly allow rendering to RGBX formats.Kenneth Graunke2019-02-251-2/+9
| | | | | | | | | | | | I was converting them at pipe_surface creation time, but not when answering queries about whether formats support rendering. This caused a lot of FBO incomplete errors for formats that ought to be supported. Fixes "Child of Light", which uses PIPE_FORMAT_R8G8B8X8_UNORM_SRGB. Also fixes Witcher 1 using wined3d (GL) according to Timur Kristóf. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109738
* iris: Drop RGBX -> RGBA for storage image usagesKenneth Graunke2019-02-251-6/+3
| | | | GLSL doesn't expose RGB/RGBX image formats, so this isn't needed.
* iris: Always use in-tree i915_drm.hJordan Justen2019-02-243-3/+3
| | | | | | | | Ref: f1374805a86 "drm-uapi: use local files, not system libdrm" Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "iris: Enable auxiliary buffer support"Kenneth Graunke2019-02-211-0/+3
| | | | | | This reverts commit cd0ced49e7957182d23e21657445b720184ea425. It breaks glxgears rendering.
* iris: Enable -msse2 and -mstackrealignKenneth Graunke2019-02-211-3/+3
| | | | | | | This is needed for gen_clflush.h intrinsics to work on 32-bit builds. i965 and anv both set these, and iris needs to as well. Tested-by: Mark Janes <[email protected]>
* iris: Enable auxiliary buffer supportKenneth Graunke2019-02-211-3/+0
| | | | | | This currently regresses KHR-GL4x.compute_shader.resource-texture, but that's a pre-existing bug (https://bugs.freedesktop.org/109113) which should be fixed up once we have fast clear support.
* iris: Flag ALL_DIRTY_BINDINGS on aux state change.Rafael Antognolli2019-02-213-21/+29
| | | | | | If we change the aux state for a given resource, we need to re-emit the binding table pointers for any stage that has such resource bound. Since we don't track that, flag IRIS_ALL_DIRTY_BINDINGS and emit all of them.
* iris: Skip resolve if there's no context.Rafael Antognolli2019-02-211-1/+9
| | | | | | If iris_resource_get_handle() gets called without a context, we can't resolve the resource. Hopefully it shouldn't be compressed anyway, so let's just add an assert to ensure it's correct.
* iris/clear: Pass on render_condition_enabled.Rafael Antognolli2019-02-211-2/+4
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* iris: Avoid leaking if we fail to allocate the aux buffer.Rafael Antognolli2019-02-211-2/+6
| | | | Otherwise we could leak the aux state map or the aux BO.
* iris: Only resolve compute resources for compute shadersKenneth Graunke2019-02-211-4/+3
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* iris: Fix aux usage in render resolve codeKenneth Graunke2019-02-211-1/+1
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* iris: Pin HiZ buffers when rendering.Rafael Antognolli2019-02-211-0/+8
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* iris: Flush before hiz_exec.Rafael Antognolli2019-02-211-0/+2
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* iris: Allow disabling aux via INTEL_DEBUG optionsKenneth Graunke2019-02-211-2/+4
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