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* iris: Use ISL_AUX_USAGE_GEN12_CCS_E on gen12Nanley Chery2020-06-191-13/+12
| | | | | | | | Makes iris pass a subtest of the fcc-write-after-clear piglit test (fast-clear tracking across layers 1 -> 0 -> 1) on gen12. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
* iris: Don't support sRGB + Y_TILED_CCS on gen9Nanley Chery2020-06-191-63/+18
| | | | | | | | Delete some code that would otherwise need updating for ISL_AUX_USAGE_GEN12_CCS_E. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
* iris: Disable sRGB fast-clears for non-0/1 valuesNanley Chery2020-06-191-15/+2
| | | | | | | | | | | | | | | | | | For texturing and draw calls, HW expects the clear color to be in two different color spaces after sRGB fast-clears - sRGB in the former and linear in the latter. Up until now, iris has stored the clear color in the sRGB color space. Limit the allowable clear colors for sRGB fast-clears to 0/1 so that both color space requirements are satisfied. Makes iris pass the sRGB -> sRGB subtest of the fcc-write-after-clear piglit test on gen9+. v2: * Drop iris_context::blend_enables. (Ken) * Drop some more resolve-related blend-state-tracking code. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
* iris: Avoid fast-clear with incompatible viewNanley Chery2020-06-191-0/+35
| | | | | | | | | | | | | | | | For rendering operations, avoid adding or using fast-cleared blocks if the render format is incompatible with the clear color interpretation. Note that the clear color is currently interpreted through the resource's surface format. Makes iris pass subtests of the fcc-write-after-clear piglit test: * UNORM -> SNORM, partial block on gen8+. * linear -> sRGB, partial block on gen9+. * UNORM -> SNORM, full block on gen12. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
* iris: Remove the CCS_D fallbackNanley Chery2020-06-191-2/+1
| | | | | | | | | | | | | | | | | | | | | | Remove the CCS_D fallback logic so that iris doesn't attempt to use a non-existent surface state for some renders. Also, add an assertion to catch the issue. The fallback in iris_resource_render_aux_usage can lead to this problem because it doesn't account for the fact that surface states created from resources with the Y_TILED_CCS modifier may only have CCS_E or NONE as aux usages (due to iris_resource_create_with_modifiers). Without this change, the next commit would have triggered the fallback and regressed the following tests on gen9: * dEQP-EGL.functional.wide_color.window_888_colorspace_srgb * dEQP-EGL.functional.wide_color.window_8888_colorspace_srgb * dEQP-EGL.functional.wide_color.pbuffer_888_colorspace_srgb * dEQP-EGL.functional.wide_color.pbuffer_8888_colorspace_srgb Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
* OPTIONAL: iris: Perform BLORP buffer barriers outside of iris_blorp_exec() hook.Francisco Jerez2020-06-031-0/+1
| | | | | | | | | | | | | | | | | | | | | The iris_blorp_exec() hook needs to be executed under a single indivisible sync region, which means that in cases where we need to emit a PIPE_CONTROL for a buffer barrier we won't be able to track the subsequent commands separately from the previous commands, which will prevent us from optimizing out subsequent PIPE_CONTROLs if we encounter the same buffers again. In particular I've encountered this situation in some SynMark test-cases which perform lots of BLORP operations with the same buffer bound as both source and destination (in order to generate mipmaps): In such a scenario if the source requires flushing we'd also end up flushing for the destination redundantly, even though a single PIPE_CONTROL would have been sufficient. This avoids a 4.5% FPS regression in SynMark OglHdrBloom and a 3.5% FPS regression in SynMark OglMultithread. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Remove iris_flush_depth_and_render_caches().Francisco Jerez2020-06-031-27/+0
| | | | | | | This helper is unused now. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Emit single render target flush PIPE_CONTROL on format mismatch.Francisco Jerez2020-06-031-1/+4
| | | | | | | | | | The big-hammer iris_flush_depth_and_render_caches() is largely redundant whenever a format mismatch is detected from iris_cache_flush_for_render(). There is no need to kick the depth, sampler nor constant caches in that case. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Open-code iris_cache_flush_for_read() and iris_cache_flush_for_depth().Francisco Jerez2020-06-031-18/+6
| | | | | | | These have become one-liners now so they can be easily inlined. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Remove render cache hash table-based synchronization.Francisco Jerez2020-06-031-42/+5
| | | | | | | | | | | The render cache hash table is now *mostly* redundant with the more general seqno matrix-based cache tracking mechanism. Most hash table operations are now gone except for the format mismatch checks done in iris_cache_flush_for_render(). Redundant code removed as a separate patch for bisectability. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Remove depth cache set tracking and synchronization.Francisco Jerez2020-06-031-20/+1
| | | | | | | | | The depth cache set is now redundant with the more general seqno matrix-based cache tracking mechanism. Removed as a separate patch for bisectability. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Remove batch argument of iris_resource_prepare_access() and friends.Francisco Jerez2020-06-031-8/+11
| | | | | | | | | | | | The resolves performed by this function are only expected to work from the render batch, so make sure we use it independently of the batch the caller wants to use. This function provides no synchronization guarantees anyway, the caller is expected to insert any cache flushing and synchronization required for the resolved surface to be visible to the target batch. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Insert buffer barrier in existing cache flush helpers.Francisco Jerez2020-06-031-0/+6
| | | | | | | | As a first step to phasing out the current hashtable-based depth and render cache tracking mechanisms. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Bracket batch operations which access memory within sync regions.Francisco Jerez2020-06-031-0/+8
| | | | | | | | | | | | | | | This delimits all batch operations which access memory between iris_batch_sync_region_start() and iris_batch_sync_region_end() calls. This makes sure that any buffer objects accessed within the region are considered in use through the same caching domain until the end of the region. Adding any buffer to the batch validation list outside of a sync region will lead to an assertion failure in a future commit, unless the caller explicitly opted out of the cache tracking mechanism. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Extend iris_context dirty state flags to 128 bits.Francisco Jerez2020-06-031-7/+11
| | | | | | | | | | | | | We're nearly out of dirty bits, and some patches pending review on GitLab no longer apply due to that. Make room for them by splitting off shader stage-specific bits into a separate stage_dirty mask. An alternative would be to split compute-related bits into a separate mask, but that would prevent the '<< stage' indexing done in various parts of the driver from working. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5279>
* iris: move iris_vtable to iris_screenMike Blumenkrantz2020-04-291-3/+3
| | | | | | | | | instead of inlining this into every context, now a struct is used in the screen struct to reduce memory usage and simplify a couple of the methods Closes: https://gitlab.freedesktop.org/kwg/mesa/-/issues/6 Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4376>
* iris: allow compression conditionally for images on gen12Tapani Pälli2020-03-161-0/+18
| | | | | | | | | | | | | | With this change, amount of resolves happening with deqp-gles31 (--deqp-case=*load_store*) drops ~50%. v2: use iris_image_view_get_format to get the format, get devinfo from context instead of passing it (Nanley) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: determine aux usage during predraw and state setupTapani Pälli2020-03-161-2/+4
| | | | | | | | | | | | | | | Patch changes surface state setup to alloc/fill states for all possible usages for image resource on gen12. Also predraw and binding table population is changed to determine correct aux usage with the new iris_image_view_aux_usage. v2: alloc always all states independent on current image aux state on gen >= 12 , code cleanups (Nanley) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: provide dummy iris_image_view_aux_usageTapani Pälli2020-03-161-0/+8
| | | | | | | | | | | | | Similar to iris_resource_texture_aux_usage this function will determine proper aux_usage for image, now it will default to ISL_AUX_USAGE_NONE. v2: drop gen_device_info parameter, rename function (Nanley) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: use the images_used mask in resolve passTapani Pälli2020-03-161-3/+3
| | | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: Use ISL_AUX_USAGE_STC_CCS for stencil CCSJason Ekstrand2020-03-121-1/+2
| | | | | Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* iris: Use ISL_AUX_USAGE_HIZ_CCS_WT to indicate write-through HiZJason Ekstrand2020-03-121-4/+7
| | | | | | | | | | | | | Previously, we always set the aux_usage to ISL_AUX_USAGE_HIZ_CCS and let ISL choose write-through based on isl_surf_supports_hiz_ccs_wt. This commit makes us choose explicitly at surface creation time whether to use HIZ_CCS or HIZ_CCS_WT based on the same set of conditions. This is more explicit and should be more robust as it lets us choose WT mode in one place rather than trusting isl_surf_supports_hiz_ccs_wt to return the same thing every time. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* iris: Use isl_aux_state_transition_write()Nanley Chery2020-02-241-182/+13
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
* iris: Use ISL's access preparation functionsNanley Chery2020-02-241-256/+34
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
* iris: Use isl_aux_usage_has_fast_clear()Nanley Chery2020-02-241-2/+2
| | | | | | | Make sure fast-clears aren't attempted or allowed for ISL_AUX_USAGE_MC. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
* iris: Allow HiZ for copy_region sourcesKenneth Graunke2020-01-041-5/+5
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Delete remnants of the unimplemented ASTC 5x5 workaroundKenneth Graunke2020-01-031-23/+5
| | | | | | | | I copy and pasted some of the boilerplate but never the implementation. For now, ASTC 5x5 is disabled and faked via uncompressed RGBA; let's delete these remnants until such a time when we implement it properly. Reviewed-by: Tapani Pälli <[email protected]>
* iris: Use mocs from isl_dev.Rafael Antognolli2019-11-121-6/+6
| | | | | Reviewed-by: Jordan Justen <[email protected]> Acked-by: Lionel Landwerlin <[email protected]>
* iris: Resolve stencil buffer lossless compression with WM_HZ_OP packetSagar Ghuge2019-10-291-9/+13
| | | | | | | | | | | | | | | | Even though stencil buffer compression looks like regular lossless color compression w/o fast clear support, we have to resolve stencil buffer with WM_HZ_OP packet. v2: Check if resource is stencil with helper function (Nanley Chery) v3: Remove unnecessary included file (Nanley Chery) v4: (Nanley Chery) - Avoid stencil buffer aux state transition by improving condition check Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Define MCS_CCS state transitions and usagesSagar Ghuge2019-10-281-5/+9
| | | | | | | | v2: 1) Fix assertion check (Nanley Chery) 2) Correct commit subject (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Enable HIZ_CCS samplingNanley Chery2019-10-281-6/+19
| | | | | Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Define initial HIZ_CCS state and transitionsNanley Chery2019-10-281-12/+18
| | | | | | | Make it match those of HIZ. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Don't assume CCS_E includes CCS_DNanley Chery2019-10-281-2/+3
| | | | | | | | There's no longer a clear-only compression mode of CCS on Gen12+. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* iris: Only resolve for image levels/layers which are actually in use.Kenneth Graunke2019-09-261-14/+12
| | | | There's no need to resolve everything.
* iris: Add infrastructure to support non coherent framebuffer fetchSagar Ghuge2019-08-201-0/+21
| | | | | | | | | | | | | | | | Create separate SURFACE_STATE for render target read in order to support non coherent framebuffer fetch on broadwell. Also we need to resolve framebuffer in order to support CCS_D. v2: Add outputs_read check (Kenneth Graunke) v3: 1) Import Curro's comment from get_isl_surf 2) Rename get_isl_surf method 3) Clean up allocation in case of failure Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Allow resolving clear color of CCS_D surfaces.Rafael Antognolli2019-07-171-6/+2
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Make iris_has_color_unresolved non-staticKenneth Graunke2019-07-171-6/+6
| | | | We want to use this in the transfer code and possibly for fast clears.
* iris: Implement INTEL_DEBUG=pc for pipe control logging.Kenneth Graunke2019-06-201-3/+10
| | | | | | | | This prints a log of every PIPE_CONTROL flush we emit, noting which bits were set, and also the reason for the flush. That way we can see which are caused by hardware workarounds, render-to-texture, buffer updates, and so on. It should make it easier to determine whether we're doing too many flushes and why.
* iris: Resolve textures used by the program, not merely bound texturesKenneth Graunke2019-05-031-2/+5
| | | | | | | | | st/mesa's PBO upload path binds a vertex shader that doesn't use any textures, but leaves the existing sampler views bound in place. This was tricking us into thinking the PBO destination might be bound for texturing in some cases. In Civilization VI, this fixes a false self- dependency issue that was preventing CCS_E compression on upload. Fixing this slightly improves frame times.
* iris: Support sRGB fast clears even if the colorspaces differ.Rafael Antognolli2019-04-301-1/+2
| | | | | | | | | | | | | | We were disabling fast clears if the view format had a different colorspace than the resource format (sRGB vs linear or vice-versa). But we actually support them if we use the view format to decide if we should encode the clear color into sRGB colorspace. Also add a missing linear -> sRGB surface format conversion (we don't want the clear color to be encoded to sRGB again during resolve). v2: Do not track sRGB colorspace during fast clears (Nanley). Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Rework image views to store pipe_image_view.Kenneth Graunke2019-04-231-1/+1
| | | | This will be useful when rebinding images.
* iris: Be less aggressive at postdraw work skippingKenneth Graunke2019-04-181-28/+36
| | | | | | | | | | | | | | | | We empty the cache sets when flushing the batch, at which point we need to add any framebuffer related BOs even though the bindings haven't changed. So, we now do the cache set tracking unconditionally. For now, we continue skipping resolve work based on the same conditions in the predraw functions - the thinking is if we didn't trigger resolves, there's nothing to update here. Time will tell if this works. Partly reverts commit 365886ebe1a54f893b688b457553eead6aa572ea, and fixes Unigine Valley rendering on Gen9+. Drops drawoverhead scores by about 10-12%. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110353
* iris: Clean up compiler warnings about unusedCaio Marcelo de Oliveira Filho2019-03-291-1/+1
| | | | | | | Removed a few unused variables and iris_getparam_boolean(). Kept 'name' around since there's a commented debug that make use of it. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Skip framebuffer resolve tracking if framebuffer isn't dirtyKenneth Graunke2019-03-211-68/+82
| | | | Improves drawoverhead baseline score by 1.86x.
* iris: Skip input resolve handling if bindings haven't changedKenneth Graunke2019-03-211-3/+12
| | | | | This brings the drawoverhead 16 Tex w/ no state change score from 22% of baseline to 97% of baseline.
* iris: Let blorp update the clear color for us.Rafael Antognolli2019-03-201-4/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Bring back check for srgb and fast clear color.Rafael Antognolli2019-03-201-3/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Make intel_hiz_exec public.Rafael Antognolli2019-03-181-1/+1
| | | | | | Need to use it for fast clearing depth buffers. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Move depth/stencil flushes so they actually do somethingKenneth Graunke2019-03-111-0/+5
| | | | | | | | | | | | | | Commit d6dd57d43cd (iris: Add missing depth cache flushes) added the depth/stencil flushes to the wrong place. I meant to add them to the iris_upload_dirty_render_state code that emits the packets, but I accidentally added them to the nearly identical looking code in iris_restore_render_saved_bos. This meant we missed the actual flushing at draw time, but instead did pointless flushing on the first draw in a batch where things are already flushed anyway. This commit moves them to iris_resolve.c, next to the depth prepares, similar to what we do for color buffers. i965 does them elsewhere, but I'm not sure why - this seems like the most consistent place.
* iris: Fix MOCS for blits and clearsKenneth Graunke2019-03-061-5/+6
| | | | I915_MOCS_CACHED is the wrong value. Expose mocs() and use that.
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