| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
|
|
|
| |
Reworks:
* free gen_buffer in gen_aux_map_buffer_free. (Rafael)
* lock around aux_map_bos accesses. (Ken)
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
|
| |
|
|
|
|
| |
Signed-off-by: Tapani Pälli <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
|
| | |
|
| |
|
|
|
|
|
|
|
|
|
|
| |
In the future, some images will need to be aligned to a larger value
than 4096. Most buffers, however, don't have any such requirement,
so for now we only add the parameter to iris_bo_alloc_tiled() and
leave the others with the simpler interface.
v2: Fix missing alignment in vma_alloc, caught by Caio!
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Tested-by: Jordan Justen <[email protected]>
|
| |
|
|
|
| |
(Chris Wilson wrote this code in a patch titled "i965: Be resilient in
the face of GPU hangs"; Ken fixed a bug and copied it to iris.)
|
| |
|
|
| |
I want to use this in iris_resource.c.
|
| |
|
|
|
|
|
|
| |
We need to preserve PIPE_TRANSFER_FLUSH_EXPLICIT, DISCARD_RANGE, and
so on, but don't want to pass them to iris_bo_map(). So, keep them all,
but mask them off when calling map.
Chris Wilson told me to do this a long time ago and he was right.
|
| |
|
|
|
|
|
|
|
| |
On !llc machines (Atoms), reading from a linear buffers is slow and so
copying from one resource into the linear staging buffer is still slow.
However, we can tell the GPU to snoop the CPU cache when reading from and
writing to the staging buffer eliminating the slow uncached reads.
Reviewed-by: Kenneth Graunke <[email protected]>
|
| |
|
|
|
| |
This now matches the actual function in iris_bufmgr.c, as well as the
equivalent brw_bufmgr.c function...
|
| |
|
|
|
|
| |
This is supposed to exclude single address zones. We were getting
too many VMA allocators but failing to set them up, which worked out
because we also forgot to destroy them...
|
| | |
|
| | |
|
| |
|
|
| |
saves a touch of cpu overhead in the new resolve tracking
|
| |
|
|
| |
nobody uses it
|
| | |
|
| | |
|
| |
|
|
|
| |
They took away our pointer bits, so now we need a pile of special code
to handle this instead of just using u_upload_mgr. :(
|
| | |
|
| | |
|
| |
|
|
| |
for wider use
|
| | |
|
| | |
|
| |
|
|
| |
for PIPE_TRANSFER_WRITE and friends
|
| |
|
|
| |
Breaks everything, woo!
|
| |
|
|
|
| |
Drop BO_ALLOC_BUSY (best not to hand people a loaded gun...)
Drop vestiges of alignment
|
| | |
|
|
|
This commit introduces a new Gallium driver for Intel Gen8+ GPUs,
named 'iris_dri.so' after the hardware.
Developed by:
- Kenneth Graunke (overall driver)
- Dave Airlie (shaders, conditional render, overflow query, Gen8 port)
- Chris Wilson (fencing, pinned memory, ...)
- Jordan Justen (compute shaders)
- Jason Ekstrand (image load store)
- Caio Marcelo de Oliveira Filho (tessellation control passthrough)
- Rafael Antognolli (auxiliary buffer fixes)
- The rest of the i965 contributors and the Mesa community
|
