| Commit message (Collapse) | Author | Age | Files | Lines |
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Add tex_create_hiz() to create HiZ bo. It is not really called yet.
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Move separate stencil allocation code to tex_create_separate_stencil to keep
tex_create sane.
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Allow HiZ op to be specified in 3DSTATE_WM. Pass depth format directly in
gen7_emit_3DSTATE_SF. Use tex->hiz.bo to determine if HiZ exists. Fix
3DSTATE_SF for the case when there is no ilo_rasterizer_state. Fix
3DSTATE_PS for the case when there is no ilo_shader_state.
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Even though the Ivy Bridge PRM lists some restrictions that require layer
offsetting as the Sandy Bridge PRM does, it seems they are actually lifted.
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GEN6 has several requirements regarding the LOD/Depth/Width/Height of the
render targets and the depth buffer. We used to offset to the layers in
question unconditionally to meet the requirements. With this commit,
offseting is done only when the requirements are not met.
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Make offset to layer optional in ilo_gpe_init_zs_surface.
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Make offset to layer optional in ilo_gpe_init_view_surface_for_texture.
render_cache_rw is always the same as is_rt and is replaced.
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Reviewed-by: Brian Paul <[email protected]>
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All bound layers (from first_layer to last_layer) should be cleared.
This uses a vertex shader which outputs gl_Layer = gl_InstanceID, so each
instance goes to a different layer. By rendering a quad and setting
the instance count to the number of layers, it will trivially clear all
layers.
This requires AMD_vertex_shader_layer (or PIPE_CAP_TGSI_VS_LAYER), which only
radeonsi supports at the moment. r600 could do this too. Standard DX11
hardware will have to use a geometry shader though, which has higher overhead.
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Ever since introducing separate sampler and sampler view max this was really
missing.
Every driver but llvmpipe reports the same number as number of samplers for
now, so nothing should break.
Reviewed-by: Jose Fonseca <[email protected]>
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* minimise flags duplication
* distingush between VISIBILITY C and CXX flags
* set only required flags - C and/or CXX
v2: add LLVM_CFLAGS back to AM_CFLAGS (add missing backslash)
Signed-off-by: Emil Velikov <[email protected]>
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Signed-off-by: Emil Velikov <[email protected]>
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[olv: use $(srcdir) instead of $(top_srcdir)]
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Kill ilo_bind_sampler_states2 and ilo_set_sampler_views2. Map
PIPE_FORMAT_R10G10B10A2_UINT to BRW_SURFACEFORMAT_R10G10B10A2_UINT.
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This CAP will determine whether ARB_framebuffer_object can be enabled.
The nv30 driver does not allow mixing swizzled and linear zsbuf/cbuf
textures.
Signed-off-by: Ilia Mirkin <[email protected]>
Signed-off-by: Marek Olšák <[email protected]>
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The new function replaces four old functions: set_fragment/vertex/
geometry/compute_sampler_views().
Note: at this time, it's expected that the 'start' parameter will
always be zero.
Reviewed-by: Roland Scheidegger <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Tested-by: Emil Velikov <[email protected]>
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r600g needs explicit flushing before DRI2 buffers are presented on the screen.
v2: add (stub) implementations for all drivers, fix frontbuffer flushing
v3: fix galahad
Signed-off-by: Marek Olšák <[email protected]>
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So that it can be hooked up pipe_context::bind_sampler_states that is
currently living on another branch.
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This is based on grepping for brw->is_haswell in i965 to see how GEN 7.5
differs from GEN 7. Slightly tested with Xonotic and some Mesa demos.
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flags to enforce no tiling.
Signed-off-by: Axel Davy <[email protected]>
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We have set up 3DSTATE_SBE (or 3DSTATE_SF on GEN6) in
ilo_shader_select_kernel_routing(). There is no need to pass the last shader
stage to the GPE function.
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Command length is ORed to the wrong place. Since the ORed value is zero,
there is no real change.
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Assert that gen6_emit_3DSTATE_CLIP is for GEN 6 and 7.
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When specified, ilo will print a line similar to
cp flushed for render with 949+888 DWords (22.4%) because of frame end
for every ilo_cp_flush() call.
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It can print out pipe_draw_info and the dirty bits set, useful for debugging.
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Signed-off-by: Christian König <[email protected]>
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Signed-off-by: Christian König <[email protected]>
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Signed-off-by: Christian König <[email protected]>
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Signed-off-by: Christian König <[email protected]>
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Missed this commit when preparing PCB changes for upstreaming.
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untested.
Reviewed-by: Chia-I Wu <[email protected]>
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This patch adds the level query support to the video decoders
and uses some more reasonable defaults.
v2: (ck) add commit message
Reviewed-by: Christian König <[email protected]>
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It was disabled because it wasn't supported.
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When constants can be pushed, and nothing else requires new SURFACE_STATEs,
there is no need to emit BINDING_TABLE_STATE.
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Source constants from URB constant data when the constant data can fit in the
PCB.
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Add ILO_KERNEL_PCB_CBUF0_SIZE so that a kernel can specify how many bytes of
constant buffer 0 need to be copied to PCB.
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Add ILO_KERNEL_SKIP_CBUF0_UPLOAD so that we can skip constant buffer 0 upload
when the kernel does not need it.
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This reverts commit a9b800aa81cffdcaef2490ff49986099feae2663. With push
constant support, the constructed SURFACE_STATE is unused and wasted. The
change only slows things down.
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Fix ilo_gpe_init_view_surface_for_buffer to allow buffer to be NULL, and add
ilo_gpe_set_view_surface_bo to set it later. This allows us to set up
SURFACE_STATE early for constant buffers backed by user buffers.
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In finalize_index_buffer(), when the current index buffer was destroyed due to
u_upload_data(), it may happen that the new index buffer is at the same
address as the old one. Comparing the pointers to the two buffers could fail
to work, and 3DSTATE_INDEX_BUFFER would be incorrectly skipped.
Holding a reference to the current index buffer before calling u_upload_data()
should fix the problem.
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Move the estimate functions out of the tables and kill the tables.
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This reduces the number of source files need to be recompiled when GPE
functions are changed other than regular clean ups.
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This could speed up BLEND_STATE and COLOR_CALC_STATE emission a bit.
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There is only one caller so fold it.
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There is only one caller so fold it.
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Eliminate pipeline and GPE function vectors and have the pipeline functions
call the GPE emit functions directly.
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