| Commit message (Collapse) | Author | Age | Files | Lines |
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We want to use ilo_dev_info instead of ilo_screen in core.
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Move what are remaining in ilo_common.h (that is, ilo_dev_*) to ilo_dev.h.
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They consist of the debug helpers that used to live in ilo_common.h and
ilo_screen.c.
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ilo_core.h includes the common gallium headers that were included in
ilo_common.h.
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Add a new subdirectory and start moving files that do not depend on
ilo_screen/ilo_context to it.
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Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Chih-Wei Huang <[email protected]>
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The only hackish ones are llvmpipe and softpipe, which currently return
the same string as for get_vendor(), while ideally they should return
the CPU vendor.
Signed-off-by: Giuseppe Bilotta <[email protected]>
Reviewed-by: Tom Stellard <[email protected]>
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We did it right until the switch to gen_surface_tiling, which has
GEN8_TILING_W. Generally, GEN8_TILING_W may be valid but not preferred.
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Add a help function for each WA and make PIPE_CONTROL flags match the WA
descriptions. Call gen6_wa_pre_pipe_contro() only before PIPE_CONTROLs.
Fix missing gen6_wa_pre_3dstate_vs_toggle() in the rectlist path.
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It replaces gen[6-8]_3dprimitive().
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It replaces gen[6-8]_pipe_control() and a direct gen6_PIPE_CONTROL() call in
ilo_render_emit_flush().
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Should use the temporary variable in the loop instead of layout->bo_height.
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interleaved_samples is only zero-initialized when layout_want_mcs() is called.
We should not check for it. There is also no need to.
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This enables L3 cache in MOCS almost everywhere.
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Scanouts require a different cache type.
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Add ilo_builder_surface_pointer() to replace ilo_builder_surface_write().
Make Gen8+ take a different path in gen6_SURFACE_STATE().
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They both check for NULL and intel_bo_ref() returns the referenced bo. They
replace intel_bo_{reference,unreference}().
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Make intel_winsys_alloc_bo() always allocate a linear bo, and add
intel_bo_set_tiling() to set the tiling. Document the purpose of tiling.
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The former is used by the kernel driver to set up fence registers and to pass
tiling info across processes. It lacks INTEL_TILING_W, which made our code
less expressive.
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The main change is non-inline <enum>s are now generated as C enums.
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Add wrappers for 3DPRIMITIVE to make sure we clear current_pipe_control_dw1
and deferred_pipe_control_dw1 after it. Add missing
gen7_wa_post_ps_and_later().
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These WAs
gen7_wa_post_3dstate_push_constant_alloc_ps()
gen7_wa_pre_vs()
gen7_wa_pre_3dstate_sf_depth_bias()
first half of gen7_wa_pre_depth()
gen7_wa_post_ps_and_later()
are Gen7-specific. Update copy-and-pasted gen8_wa_pre_depth() also.
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When set, detect and dump the hanging batch bufffer.
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Add intel_winsys_get_reset_stats(), intel_winsys_import_userptr(), and
intel_bo_map_async(). The latter two are stubs, but we are not going to use
them immediately either.
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Gen8+ must use VALIGN_4. Unlike prior Gens, R32G32B32_FLOAT should supposedly
support VALIGN_4.
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The restriction is lifted.
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GT3 has two slices and all limits are doubled.
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Fix -Wmaybe-uninitialized warnings. The change to
ilo_blit_resolve_slices_for_hiz() is a potential bug fix.
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v2: add alignment restrictions to docs, fix indentation in headers
Reviewed-by: Christian König <[email protected]>
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There is now an DW0 that seems to be always referenced.
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Shoudl use GEN8_BLEND_DW0_ALPHA_TEST_ENABLE instead of
GEN6_RT_DW1_ALPHA_TEST_ENABLE (and others).
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3DSTATE_CC_STATE_POINTERS seems to be ignored when bit 0 of DW1 is not set.
Follow i965 and set the bit for 3DSTATE_CC_STATE_POINTERS and
3DSTATE_BLEND_STATE_POINTERS. Add gen checks for all state pointer commands.
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UIP is in DW2 and JIP is in DW3 on Gen8. Also, the units are in bytes.
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It is not needed on Gen6+, and it appears to be broken on Gen8.
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JIP is int32_t and UIP is in DW2 on Gen8.
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Replace imm32 by imm64. Add more ways (UD, D, etc) to access the immediate.
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Decode the higher and lower 16 bits separately.
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Add disasm_inst_decode_dw0_opcode_gen6() to decode the opcode. Simplify
branch_ctrl/acc_wr_ctrl decoding.
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Update gen checks for 3DSTATE_POLY_STIPPLE_OFFSET,
3DSTATE_POLY_STIPPLE_PATTERN, 3DSTATE_LINE_STIPPLE, and
3DSTATE_AA_LINE_PARAMETERS.
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5 PIPE_CONTROLs, 2 3DSTATE_WM_HZ_OP, and depth buffer setup require 65 DWords.
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The pipe primitive type was wrongly translated twice.
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This is very preliminary and is only tested with glxgears. All information
about Gen8 is derived from i965 and beignet.
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