| Commit message (Collapse) | Author | Age | Files | Lines |
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This can be derived from the shader caps.
All GPUs from ATI/AMD, NVIDIA, and INTEL have separate texture slots
for each shader stage.
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Ian manually ran the map_buffer_range* tests and the
arb_map_buffer_alignment-* tests, but he did not do a full piglit run.
v2 (idr): Use 64 instead of 4096
Tested-by: Ian Romanick <[email protected]>
Reviewed-by: Chia-I Wu <[email protected]>
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If any driver doesn't support this, it can use a blit after resolving
the samples.
Reviewed-by: Brian Paul <[email protected]>
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Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the
old copyright name is creating unnecessary confusion, hence this change.
This was the sed script I used:
$ cat tg2vmw.sed
# Run as:
#
# git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed
#
# Rename copyrights
s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g
/Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./
s/TUNGSTEN GRAPHICS/VMWARE/g
# Rename emails
s/[email protected]/[email protected]/
s/[email protected]/[email protected]/g
s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/
s/jrfonseca\[email protected]/[email protected]/g
s/keithw\[email protected]/[email protected]/g
s/[email protected]/[email protected]/g
s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/
s/[email protected]/[email protected]/
# Remove dead links
s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g
# C string src/gallium/state_trackers/vega/api_misc.c
s/"Tungsten Graphics, Inc"/"VMware, Inc"/
Reviewed-by: Brian Paul <[email protected]>
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Renderbuffers may be NULL since 9baa45f78b8ca7d66280e36009b6a685055d7cd6.
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We need to disable HiZ for non-8x4 aligned levels, except for level 0, layer
0. For the very first layer we can adjust Width and Height fields of
3DSTATE_DEPTH_BUFFER to make it aligned.
Specifically, add ILO_TEXTURE_HIZ and set the flag only for properly aligned
levels. ilo_texture_can_enable_hiz() is updated to check for the flag.
In tex_layout_validate(), align the depth bo to 8x4 so that we can adjust
Width/Height of 3DSTATE_DEPTH_BUFFER without introducing out-of-bound access.
Finally in rectlist blitter, add the ability to adjust 3DSTATE_DEPTH_BUFFER.
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Add ilo_texture_can_enable_hiz and replace all checks for tex->hiz.bo by calls
to ilo_texture_can_enable_hiz().
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Add tex_layout_init_hiz() before tex_layout_init_format() to decide whether
HiZ should be enabled.
On GEN6, because of layer offsetting, HiZ is enabled only when the texture is
non-mipmapped and non-array. PIPE_USAGE_STAGING is also taken as a hint to
disable HiZ.
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Rename the workaround, as it is for 3DSTATE_PS instead of 3DSTATE_WM, and emit
it on Haswell too.
This does not fix any app, but an assertion failure.
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The comment was no longer true since 6642381e7513926b847d6bc10bf590e1c0c54859.
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On GEN6, HiZ and Separate Stencil Buffer must be enabled at the same time.
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Dereference the HiZ bo when the texture is destroyed.
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Call ilo_texture_get_slice() for the last slice so that we can get rid of the
duplicated assert().
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The support is still early. Fast depth buffer clear is not enabled yet.
HiZ can be forced off with ILO_DEBUG=nohiz.
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When the depth buffer is to be read, perform a Depth Buffer Resolve if it has
been rendered. When the depth buffer is to be rendered, perform a HiZ Buffer
Resolve when the depth buffer is modified externally.
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The flags are used to mark who (CPU, BLT, or RENDER) has accessed the resource
and how (READ or WRITE).
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Rename ilo_texture::slice_offsets to ilo_texture::slices and add an accessor,
ilo_texture_get_slice().
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Add blitter functions to perform Depth Buffer Clear, Depth Buffer Resolve, and
Hierarchical Depth Buffer Resolve. Those functions set ilo_blitter up and
pass it to the pipelines to emit the commands.
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Add tex_create_hiz() to create HiZ bo. It is not really called yet.
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Move separate stencil allocation code to tex_create_separate_stencil to keep
tex_create sane.
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Allow HiZ op to be specified in 3DSTATE_WM. Pass depth format directly in
gen7_emit_3DSTATE_SF. Use tex->hiz.bo to determine if HiZ exists. Fix
3DSTATE_SF for the case when there is no ilo_rasterizer_state. Fix
3DSTATE_PS for the case when there is no ilo_shader_state.
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Even though the Ivy Bridge PRM lists some restrictions that require layer
offsetting as the Sandy Bridge PRM does, it seems they are actually lifted.
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GEN6 has several requirements regarding the LOD/Depth/Width/Height of the
render targets and the depth buffer. We used to offset to the layers in
question unconditionally to meet the requirements. With this commit,
offseting is done only when the requirements are not met.
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Make offset to layer optional in ilo_gpe_init_zs_surface.
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Make offset to layer optional in ilo_gpe_init_view_surface_for_texture.
render_cache_rw is always the same as is_rt and is replaced.
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Reviewed-by: Brian Paul <[email protected]>
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All bound layers (from first_layer to last_layer) should be cleared.
This uses a vertex shader which outputs gl_Layer = gl_InstanceID, so each
instance goes to a different layer. By rendering a quad and setting
the instance count to the number of layers, it will trivially clear all
layers.
This requires AMD_vertex_shader_layer (or PIPE_CAP_TGSI_VS_LAYER), which only
radeonsi supports at the moment. r600 could do this too. Standard DX11
hardware will have to use a geometry shader though, which has higher overhead.
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Ever since introducing separate sampler and sampler view max this was really
missing.
Every driver but llvmpipe reports the same number as number of samplers for
now, so nothing should break.
Reviewed-by: Jose Fonseca <[email protected]>
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* minimise flags duplication
* distingush between VISIBILITY C and CXX flags
* set only required flags - C and/or CXX
v2: add LLVM_CFLAGS back to AM_CFLAGS (add missing backslash)
Signed-off-by: Emil Velikov <[email protected]>
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Signed-off-by: Emil Velikov <[email protected]>
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[olv: use $(srcdir) instead of $(top_srcdir)]
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Kill ilo_bind_sampler_states2 and ilo_set_sampler_views2. Map
PIPE_FORMAT_R10G10B10A2_UINT to BRW_SURFACEFORMAT_R10G10B10A2_UINT.
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This CAP will determine whether ARB_framebuffer_object can be enabled.
The nv30 driver does not allow mixing swizzled and linear zsbuf/cbuf
textures.
Signed-off-by: Ilia Mirkin <[email protected]>
Signed-off-by: Marek Olšák <[email protected]>
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The new function replaces four old functions: set_fragment/vertex/
geometry/compute_sampler_views().
Note: at this time, it's expected that the 'start' parameter will
always be zero.
Reviewed-by: Roland Scheidegger <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Tested-by: Emil Velikov <[email protected]>
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r600g needs explicit flushing before DRI2 buffers are presented on the screen.
v2: add (stub) implementations for all drivers, fix frontbuffer flushing
v3: fix galahad
Signed-off-by: Marek Olšák <[email protected]>
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So that it can be hooked up pipe_context::bind_sampler_states that is
currently living on another branch.
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This is based on grepping for brw->is_haswell in i965 to see how GEN 7.5
differs from GEN 7. Slightly tested with Xonotic and some Mesa demos.
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flags to enforce no tiling.
Signed-off-by: Axel Davy <[email protected]>
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We have set up 3DSTATE_SBE (or 3DSTATE_SF on GEN6) in
ilo_shader_select_kernel_routing(). There is no need to pass the last shader
stage to the GPE function.
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Command length is ORed to the wrong place. Since the ORed value is zero,
there is no real change.
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Assert that gen6_emit_3DSTATE_CLIP is for GEN 6 and 7.
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When specified, ilo will print a line similar to
cp flushed for render with 949+888 DWords (22.4%) because of frame end
for every ilo_cp_flush() call.
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It can print out pipe_draw_info and the dirty bits set, useful for debugging.
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Signed-off-by: Christian König <[email protected]>
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Signed-off-by: Christian König <[email protected]>
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Signed-off-by: Christian König <[email protected]>
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Signed-off-by: Christian König <[email protected]>
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