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* gallium: remove PIPE_SHADER_CAP_MAX_ADDRSMarek Olšák2014-08-111-2/+0
| | | | | | | | | | | | | | | This limit is fixed in Mesa core and cannot be changed. It only affects ARB_vertex_program and ARB_fragment_program. The minimum value for ARB_vertex_program is 1 according to the spec. The maximum value for ARB_vertex_program is limited to 1 by Mesa core. The value should be zero for ARB_fragment_program, because it doesn't support ARL. Finally, drivers shouldn't mess with these values arbitrarily. Reviewed-by: Ilia Mirkin <[email protected]>
* ilo: break down the format tableChia-I Wu2014-08-081-299/+431
| | | | | | | The PRMs no longer have a single table for format capabilities. Multiple tables take up less space, and are easier to maintain. Encode typed write information while at it.
* ilo: fix fb height of HiZ opsChia-I Wu2014-07-291-1/+1
| | | | | It was set to aligned width. It appears to be fine on GEN7+, but causes random hangs on GEN6.
* gallium: rename shader cap MAX_CONSTS to MAX_CONST_BUFFER_SIZEMarek Olšák2014-07-281-2/+2
| | | | | | | | | | This new name isn't so confusing. I also changed the gallivm limit, because it looked wrong. Reviewed-by: Brian Paul <[email protected]> v2: use sizeof(float[4])
* ilo: correctly propagate resource renames to hardwareChia-I Wu2014-07-283-14/+30
| | | | | Not only should we mark states dirty when the underlying resource is renamed, we should also update the CSO bo when available.
* ilo: add ilo_resource_get_bo() helperChia-I Wu2014-07-282-17/+18
| | | | We will need it in the following commit.
* ilo: unblock an inline write with a staging boChia-I Wu2014-07-281-13/+31
| | | | This should allow a deeper pipeline.
* ilo: try unblocking a transfer with a staging boChia-I Wu2014-07-284-19/+209
| | | | | | | When mapping a busy resource with PIPE_TRANSFER_DISCARD_RANGE or PIPE_TRANSFER_FLUSH_EXPLICIT, we can avoid blocking by allocating and mapping a staging bo, and emit pipelined copies at proper places. Since the staging bo is never bound to GPU, we give it packed layout to save space.
* ilo: enable persistent and coherent transfersChia-I Wu2014-07-283-8/+35
| | | | Enable PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT and reorder caps a bit.
* ilo: drop ptr from ilo_transferChia-I Wu2014-07-282-35/+36
| | | | | With the recent clean-ups, we can pass the mapped pointer around between functions cleanly. Drop it to make ilo_transfer smaller.
* ilo: s/TRANSFER_MAP_UNSYNC/TRANSFER_MAP_GTT_UNSYNC/Chia-I Wu2014-07-282-6/+6
| | | | | It maps to drm_intel_gem_bo_map_unsynchronized(), which results in unsynchronized GTT mapping.
* ilo: drop unused context param from transfer functionsChia-I Wu2014-07-281-115/+100
| | | | Many of the transfer functions do not need an ilo_context. Drop it.
* ilo: tidy up transfer mapping/unmappingChia-I Wu2014-07-281-88/+89
| | | | | | Add xfer_map() to replace map_bo_for_transfer(). Add xfer_unmap() and xfer_alloc_staging_sys() to simplify texture and buffer mapping/unmapping, and enable more code sharing between them.
* ilo: tidy up choose_transfer_method()Chia-I Wu2014-07-281-84/+164
| | | | | | Add a bunch of helper functions and a big comment for choose_transfer_method(). This also fixes handling of PIPE_TRANSFER_MAP_DIRECTLY to not ignore tiling.
* ilo: free transfers with util_slab_free()Chia-I Wu2014-07-281-1/+1
| | | | We used FREE() in one of the error path.
* ilo: simplify ilo_flush()Chia-I Wu2014-07-263-20/+30
| | | | Move fence creation to the new ilo_fence_create().
* ilo: check the tilings of imported handlesChia-I Wu2014-07-241-30/+36
| | | | Just to be cautious.
* ilo: clean up resource bo renamingChia-I Wu2014-07-244-51/+63
| | | | | s/alloc_bo/rename_bo/ as that is what the functions do. Simplify bo allocation and move the complexity to bo renaming.
* ilo: share some code between {tex,buf}_create_boChia-I Wu2014-07-241-59/+55
| | | | | Add resource_get_bo_name() and resource_get_bo_initial_domain() for use by both functions.
* ilo: use native 3-component vertex formats on GEN7.5+Chia-I Wu2014-07-242-1/+6
| | | | GEN7.5 gains support for those formats natively.
* ilo: allow for device-dependent format translationChia-I Wu2014-07-245-32/+39
| | | | Pass ilo_dev_info to all format translation functions.
* ilo: add some missing formatsChia-I Wu2014-07-161-21/+22
| | | | Map more pipe formats to hardware formats. Enable more VB formats on Haswell.
* ilo: update and tailor the surface format tableChia-I Wu2014-07-161-286/+258
| | | | | Recreate the table from scratch with the help of a pdf-table-to-csv converter. Switch to a form that is more suitable for ilo.
* ilo: raise texture size limitsChia-I Wu2014-07-152-17/+9
| | | | | Report the hardware limits now that max-texture-size piglit test has been fixed.
* ilo: move away from drm_intel_bo_alloc_tiledChia-I Wu2014-07-153-250/+300
| | | | | We want to know the exact sizes of the BOs, and the driver has the knowledge to do so. Refactoring of the resource allocation code is needed though.
* gallium: switch dedicated centroid field to interpolation locationIlia Mirkin2014-07-091-1/+1
| | | | | | | | The new location field can be either center, centroid, or sample, which indicates the location that the shader should interpolate at. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* ilo: fix fence reference countingChia-I Wu2014-07-081-12/+9
| | | | The old code was complicated, and was wrong when *ptr is NULL.
* gallium: rename PIPE_CAP_TGSI_VS_LAYER to also have _VIEWPORTIlia Mirkin2014-07-031-1/+1
| | | | | | | | | Now that this cap is used to determine the availability of both, adjust its name to reflect the new reality. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add a cap for max vertex streamsIlia Mirkin2014-07-011-0/+1
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add an index argument to create_queryIlia Mirkin2014-07-011-1/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: create TGSI_PROPERTY to disable viewport and clippingChristoph Bumiller2014-06-021-0/+1
| | | | | | Marek v2: add a cap Signed-off-by: Marek Olšák <[email protected]>
* gallium: add a cap for supporting 4-offset TG4 opcodesIlia Mirkin2014-05-071-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add basic support for ARB_sample_shadingIlia Mirkin2014-04-261-0/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/util: use ui[4] instead of ui in union util_colorRoland Scheidegger2014-04-251-2/+2
| | | | | | | | util_color often merely represents a collection of bytes, however it is inconvenient if those bytes can only be accessed as floats/doubles for int formats exceeding 32bits. (Note that since rgba8 formats use one uint, not 4 bytes, hence the byte and short member were left as is.)
* ilo: remove GPE state size estimationChia-I Wu2014-04-147-326/+97
| | | | Use size defines from genhw.
* ilo: remove GPE command size estimationChia-I Wu2014-04-146-403/+87
| | | | Use size defines from genhw.
* ilo: remove unused headersChia-I Wu2014-04-143-566/+0
| | | | | Remove intel_*.h. brw_*.h is still needed by the state dumper and disassembler.
* ilo: use only defines from genhw headersChia-I Wu2014-04-147-106/+87
| | | | Stop including classic driver headers in genhw.h, with some formatting fixes.
* ilo: scripted conversion to genhw headersChia-I Wu2014-04-1425-1626/+1626
| | | | Hopefully my four hundred line sed script is correct.
* ilo: add genhw headersChia-I Wu2014-04-1422-131/+3504
| | | | | All except genhw.h are generated by https://github.com/olvaffe/envytools/. intel_chipset.h is deprecated.
* ilo: avoid brw_wm_barycentric_interp_mode in compilerChia-I Wu2014-04-141-17/+46
| | | | In preparation for genhw.
* ilo: add TOY_OPCODE_DOChia-I Wu2014-04-146-7/+10
| | | | | We used to give BRW_OPCODE_DO a special meaning, while we should have used TOY_OPCODE_DO.
* gallium: add a way to query min/max texture gather offsetsIlia Mirkin2014-04-101-0/+2
| | | | | | | | Defaults to providing the same offsets as MIN/MAX_TEXEL_OFFSET. For nvc0, the offset can be -32/31. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add support for LODQ opcodes.Dave Airlie2014-04-071-0/+1
| | | | | | | | | This opcode provide support for GL_ARB_texture_query_lod, Signed-off-by: Dave Airlie <[email protected]> [imirkin: rebase, docs update] Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/soft/llvmpipe: add fake MSAA supportDave Airlie2014-04-021-0/+1
| | | | | | | | This adds a gallium cap that allows us to fake GL3.0 by not exposing MSAA on sw rendering. It also forces the extra extensions needed for GL3.2. Signed-off-by: Dave Airlie <[email protected]>
* gallium: allow setting of the internal stream output offsetZack Rusin2014-03-071-2/+6
| | | | | | | | | | | | | | | | D3D10 allows setting of the internal offset of a buffer, which is in general only incremented via actual stream output writes. By allowing setting of the internal offset draw_auto is capable of rendering from buffers which have not been actually streamed out to. Our interface didn't allow. This change functionally shouldn't make any difference to OpenGL where instead of an append_bitmask you just get a real array where -1 means append (like in D3D) and 0 means do not append. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ilo: add support for PIPE_QUERY_PIPELINE_STATISTICSChia-I Wu2014-03-104-3/+108
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* ilo: add ILO_3D_PIPELINE_WRITE_STATISTICSChia-I Wu2014-03-105-0/+90
| | | | The command writes statistics registers to the specified bo.
* ilo: add some MI commands to GPEChia-I Wu2014-03-104-0/+116
| | | | We will need MI commands that load/store registers.
* ilo: set PIPE_CONTROL_GLOBAL_GTT_WRITE automaticallyChia-I Wu2014-03-102-2/+16
| | | | | Set the flag automatically in gen6_emit_PIPE_CONTROL(), and set it only for GEN6.
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