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* ilo: set INTEL_RELOC_GGTT only on GEN6Chia-I Wu2014-08-311-7/+17
| | | | We asked MI commands to use GGTT only on GEN6.
* ilo: fix bound check for 3DSTATE_URB_VSChia-I Wu2014-08-311-3/+3
| | | | Fix max/min entries on GEN7.5 GT2/GT3.
* ilo: replace cmd by dw0 in GPEChia-I Wu2014-08-312-167/+236
| | | | | With e3c251071b0c9396c3ec76d1cf943c60ae297281, the magic values are gone. We no longer need "cmd" to hide them. Replace it by dw0.
* gallium/ilo: cleanup intel_winsys.hEmil Velikov2014-08-283-3/+312
| | | | | | | | | | | | | | | | Make the header location, inclusion and contents more common with its i915,r* and nouveau counterparts: - Move the header within drivers/ilo. - Separate out intel_winsys_create_for_fd into 'drm_public' header. - Cleanup the compiler includes. v2: Move the header to drivers/ilo. Suggested by Chia-I. v3: Correct intel_winsys.h inclusion. Spotted by Chia-I. Cc: Chia-I Wu <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* gallium: add cap for MAX_VERTEX_ATTRIB_STRIDETimothy Arceri2014-08-271-0/+2
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* ilo: use genhw command opcodesChia-I Wu2014-08-265-134/+184
| | | | | Replace ILO_GPE_MI and ILO_GPE_CMD with magic values by descriptive genhw macros.
* ilo: rename intel_bo_map_unsynchronized()Chia-I Wu2014-08-262-9/+8
| | | | Rename it to intel_bo_map_gtt_async().
* ilo: remove max_batch_sizeChia-I Wu2014-08-263-8/+1
| | | | | It is used to derive an artificial limit on max relocs per bo. We choose not to export it anymore.
* ilo: replace domains by reloc flagsChia-I Wu2014-08-269-93/+47
| | | | | It is simpler and is supported by the kernel. It cannot be used with libdrm_intel yet though.
* gallium: Add and handle PIPE_CAP_CONDITIONAL_RENDER_INVERTEDTobias Klausmann2014-08-191-0/+1
| | | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* ilo: fix PIPE_CAP_VIDEO_MEMORYChia-I Wu2014-08-191-2/+2
| | | | | | I changed Emil's patch in f921131a5cebc233749a86cdd44b409c0cecc4ef to report raw values in the winsys, but forgot to convert the values to megabytes in the pipe driver.
* ilo: enable HiZ in more cases on GEN6Chia-I Wu2014-08-193-31/+44
| | | | | With layer offsetting killed, we no longer need to restrict HiZ to non-mipmapped and non-arary depth buffers.
* ilo: remove layer offsettingChia-I Wu2014-08-197-393/+27
| | | | Follow i965 to kill layer offsetting for GEN6.
* ilo: migrate to ilo_layoutChia-I Wu2014-08-198-1454/+213
| | | | Embed an ilo_layout in ilo_texture, and remove now duplicated members.
* ilo: add new resource layout codeChia-I Wu2014-08-193-0/+1779
| | | | | | | Based on the old code, the new layout code describes the layout with the new, well-documented, ilo_layout. It also gains new features such as MCS support and extended ARYSPC_LOD0 that i965 comes up with (see 6345a94a9b134b1321b3b290bacde228b12af415).
* ilo: fold drm_intel_get_aperture_sizes() within probe_winsys()Emil Velikov2014-08-192-2/+5
| | | | | | | | | ... and store the value in intel_winsys_info/ilo_dev_info. Suggested-by: Chia-I Wu <[email protected]> Signed-off-by: Emil Velikov <[email protected]> olv: check for errors and report raw values
* gallium/ilo: handle query_renderer capsEmil Velikov2014-08-151-0/+24
| | | | | | | | | | | Implementation based on the classic driver with the following changes: - Use auxiliarry function os_get_total_physical_memory to get the total amount of memory. - Move the libdrm_intel specific get_aperture_size to the winsys. Cc: Chia-I Wu <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* gallium: add opcodes/cap for fine derivative supportIlia Mirkin2014-08-141-0/+1
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) Reviewed-by: Roland Scheidegger <[email protected]> (v1) v2: Reuse opcode gaps as suggested by Marek
* gallium: remove PIPE_SHADER_CAP_MAX_ADDRSMarek Olšák2014-08-111-2/+0
| | | | | | | | | | | | | | | This limit is fixed in Mesa core and cannot be changed. It only affects ARB_vertex_program and ARB_fragment_program. The minimum value for ARB_vertex_program is 1 according to the spec. The maximum value for ARB_vertex_program is limited to 1 by Mesa core. The value should be zero for ARB_fragment_program, because it doesn't support ARL. Finally, drivers shouldn't mess with these values arbitrarily. Reviewed-by: Ilia Mirkin <[email protected]>
* ilo: break down the format tableChia-I Wu2014-08-081-299/+431
| | | | | | | The PRMs no longer have a single table for format capabilities. Multiple tables take up less space, and are easier to maintain. Encode typed write information while at it.
* ilo: fix fb height of HiZ opsChia-I Wu2014-07-291-1/+1
| | | | | It was set to aligned width. It appears to be fine on GEN7+, but causes random hangs on GEN6.
* gallium: rename shader cap MAX_CONSTS to MAX_CONST_BUFFER_SIZEMarek Olšák2014-07-281-2/+2
| | | | | | | | | | This new name isn't so confusing. I also changed the gallivm limit, because it looked wrong. Reviewed-by: Brian Paul <[email protected]> v2: use sizeof(float[4])
* ilo: correctly propagate resource renames to hardwareChia-I Wu2014-07-283-14/+30
| | | | | Not only should we mark states dirty when the underlying resource is renamed, we should also update the CSO bo when available.
* ilo: add ilo_resource_get_bo() helperChia-I Wu2014-07-282-17/+18
| | | | We will need it in the following commit.
* ilo: unblock an inline write with a staging boChia-I Wu2014-07-281-13/+31
| | | | This should allow a deeper pipeline.
* ilo: try unblocking a transfer with a staging boChia-I Wu2014-07-284-19/+209
| | | | | | | When mapping a busy resource with PIPE_TRANSFER_DISCARD_RANGE or PIPE_TRANSFER_FLUSH_EXPLICIT, we can avoid blocking by allocating and mapping a staging bo, and emit pipelined copies at proper places. Since the staging bo is never bound to GPU, we give it packed layout to save space.
* ilo: enable persistent and coherent transfersChia-I Wu2014-07-283-8/+35
| | | | Enable PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT and reorder caps a bit.
* ilo: drop ptr from ilo_transferChia-I Wu2014-07-282-35/+36
| | | | | With the recent clean-ups, we can pass the mapped pointer around between functions cleanly. Drop it to make ilo_transfer smaller.
* ilo: s/TRANSFER_MAP_UNSYNC/TRANSFER_MAP_GTT_UNSYNC/Chia-I Wu2014-07-282-6/+6
| | | | | It maps to drm_intel_gem_bo_map_unsynchronized(), which results in unsynchronized GTT mapping.
* ilo: drop unused context param from transfer functionsChia-I Wu2014-07-281-115/+100
| | | | Many of the transfer functions do not need an ilo_context. Drop it.
* ilo: tidy up transfer mapping/unmappingChia-I Wu2014-07-281-88/+89
| | | | | | Add xfer_map() to replace map_bo_for_transfer(). Add xfer_unmap() and xfer_alloc_staging_sys() to simplify texture and buffer mapping/unmapping, and enable more code sharing between them.
* ilo: tidy up choose_transfer_method()Chia-I Wu2014-07-281-84/+164
| | | | | | Add a bunch of helper functions and a big comment for choose_transfer_method(). This also fixes handling of PIPE_TRANSFER_MAP_DIRECTLY to not ignore tiling.
* ilo: free transfers with util_slab_free()Chia-I Wu2014-07-281-1/+1
| | | | We used FREE() in one of the error path.
* ilo: simplify ilo_flush()Chia-I Wu2014-07-263-20/+30
| | | | Move fence creation to the new ilo_fence_create().
* ilo: check the tilings of imported handlesChia-I Wu2014-07-241-30/+36
| | | | Just to be cautious.
* ilo: clean up resource bo renamingChia-I Wu2014-07-244-51/+63
| | | | | s/alloc_bo/rename_bo/ as that is what the functions do. Simplify bo allocation and move the complexity to bo renaming.
* ilo: share some code between {tex,buf}_create_boChia-I Wu2014-07-241-59/+55
| | | | | Add resource_get_bo_name() and resource_get_bo_initial_domain() for use by both functions.
* ilo: use native 3-component vertex formats on GEN7.5+Chia-I Wu2014-07-242-1/+6
| | | | GEN7.5 gains support for those formats natively.
* ilo: allow for device-dependent format translationChia-I Wu2014-07-245-32/+39
| | | | Pass ilo_dev_info to all format translation functions.
* ilo: add some missing formatsChia-I Wu2014-07-161-21/+22
| | | | Map more pipe formats to hardware formats. Enable more VB formats on Haswell.
* ilo: update and tailor the surface format tableChia-I Wu2014-07-161-286/+258
| | | | | Recreate the table from scratch with the help of a pdf-table-to-csv converter. Switch to a form that is more suitable for ilo.
* ilo: raise texture size limitsChia-I Wu2014-07-152-17/+9
| | | | | Report the hardware limits now that max-texture-size piglit test has been fixed.
* ilo: move away from drm_intel_bo_alloc_tiledChia-I Wu2014-07-153-250/+300
| | | | | We want to know the exact sizes of the BOs, and the driver has the knowledge to do so. Refactoring of the resource allocation code is needed though.
* gallium: switch dedicated centroid field to interpolation locationIlia Mirkin2014-07-091-1/+1
| | | | | | | | The new location field can be either center, centroid, or sample, which indicates the location that the shader should interpolate at. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* ilo: fix fence reference countingChia-I Wu2014-07-081-12/+9
| | | | The old code was complicated, and was wrong when *ptr is NULL.
* gallium: rename PIPE_CAP_TGSI_VS_LAYER to also have _VIEWPORTIlia Mirkin2014-07-031-1/+1
| | | | | | | | | Now that this cap is used to determine the availability of both, adjust its name to reflect the new reality. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add a cap for max vertex streamsIlia Mirkin2014-07-011-0/+1
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add an index argument to create_queryIlia Mirkin2014-07-011-1/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: create TGSI_PROPERTY to disable viewport and clippingChristoph Bumiller2014-06-021-0/+1
| | | | | | Marek v2: add a cap Signed-off-by: Marek Olšák <[email protected]>
* gallium: add a cap for supporting 4-offset TG4 opcodesIlia Mirkin2014-05-071-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
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