| Commit message (Collapse) | Author | Age | Files | Lines |
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r600g needs explicit flushing before DRI2 buffers are presented on the screen.
v2: add (stub) implementations for all drivers, fix frontbuffer flushing
v3: fix galahad
Signed-off-by: Marek Olšák <[email protected]>
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So that it can be hooked up pipe_context::bind_sampler_states that is
currently living on another branch.
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This is based on grepping for brw->is_haswell in i965 to see how GEN 7.5
differs from GEN 7. Slightly tested with Xonotic and some Mesa demos.
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flags to enforce no tiling.
Signed-off-by: Axel Davy <[email protected]>
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We have set up 3DSTATE_SBE (or 3DSTATE_SF on GEN6) in
ilo_shader_select_kernel_routing(). There is no need to pass the last shader
stage to the GPE function.
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Command length is ORed to the wrong place. Since the ORed value is zero,
there is no real change.
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Assert that gen6_emit_3DSTATE_CLIP is for GEN 6 and 7.
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When specified, ilo will print a line similar to
cp flushed for render with 949+888 DWords (22.4%) because of frame end
for every ilo_cp_flush() call.
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It can print out pipe_draw_info and the dirty bits set, useful for debugging.
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Signed-off-by: Christian König <[email protected]>
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Signed-off-by: Christian König <[email protected]>
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Signed-off-by: Christian König <[email protected]>
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Signed-off-by: Christian König <[email protected]>
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Missed this commit when preparing PCB changes for upstreaming.
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untested.
Reviewed-by: Chia-I Wu <[email protected]>
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This patch adds the level query support to the video decoders
and uses some more reasonable defaults.
v2: (ck) add commit message
Reviewed-by: Christian König <[email protected]>
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It was disabled because it wasn't supported.
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When constants can be pushed, and nothing else requires new SURFACE_STATEs,
there is no need to emit BINDING_TABLE_STATE.
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Source constants from URB constant data when the constant data can fit in the
PCB.
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Add ILO_KERNEL_PCB_CBUF0_SIZE so that a kernel can specify how many bytes of
constant buffer 0 need to be copied to PCB.
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Add ILO_KERNEL_SKIP_CBUF0_UPLOAD so that we can skip constant buffer 0 upload
when the kernel does not need it.
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This reverts commit a9b800aa81cffdcaef2490ff49986099feae2663. With push
constant support, the constructed SURFACE_STATE is unused and wasted. The
change only slows things down.
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Fix ilo_gpe_init_view_surface_for_buffer to allow buffer to be NULL, and add
ilo_gpe_set_view_surface_bo to set it later. This allows us to set up
SURFACE_STATE early for constant buffers backed by user buffers.
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In finalize_index_buffer(), when the current index buffer was destroyed due to
u_upload_data(), it may happen that the new index buffer is at the same
address as the old one. Comparing the pointers to the two buffers could fail
to work, and 3DSTATE_INDEX_BUFFER would be incorrectly skipped.
Holding a reference to the current index buffer before calling u_upload_data()
should fix the problem.
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Move the estimate functions out of the tables and kill the tables.
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This reduces the number of source files need to be recompiled when GPE
functions are changed other than regular clean ups.
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This could speed up BLEND_STATE and COLOR_CALC_STATE emission a bit.
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There is only one caller so fold it.
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There is only one caller so fold it.
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Eliminate pipeline and GPE function vectors and have the pipeline functions
call the GPE emit functions directly.
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Ignore vbuffer_mask which does not gain us anything.
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When the number of sampler states bound is reduced, we are good to keep
referencing the old SAMPLER_STATE array and skip emitting a new one.
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Remove the special path that unbinds all samplers/views not in the range.
Just make another call to unbind them.
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I intended to do a memcmp(), not a memcpy()...
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Cc: [email protected]
[ Francisco Jerez: Fix "PIPE_ENDIAN_SMALL" in the documentation,
define PIPE_ENDIAN_NATIVE. ]
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When only the offset to the index buffer is changed, we can skip the
3DSTATE_INDEX_BUFFER if we always use 0 for the offset, and add
(offset / index_size) to Start Vertex Location in 3DPRIMITIVE.
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The compiler does not know that ilo_3d_pipeline_estimate_size() is pure and
can be eliminated in a release build in gen6_pipeline_end(). Move the call
into the assert().
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The checks may seem redundant because cso_context handles them, but
util_blitter does not have access to cso_context.
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Document why certain states need to be saved, and fix a bug when blitting with
scissor enabled.
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TGSI_OPCODE_KIL and KILP had confusing names. The former was conditional
kill (if any src component < 0). The later was unconditional kill.
At one time KILP was supposed to work with NV-style condition
codes/predicates but we never had that in TGSI.
This patch renames both opcodes:
TGSI_OPCODE_KIL -> KILL_IF (kill if src.xyzw < 0)
TGSI_OPCODE_KILP -> KILL (unconditional kill)
Note: I didn't just transpose the opcode names to help ensure that I
didn't miss updating any code anywhere.
I believe I've updated all the relevant code and comments but I'm
not 100% sure that some drivers had this right in the first place.
For example, the radeon driver might have llvm.AMDGPU.kill and
llvm.AMDGPU.kilp mixed up. Driver authors should review their code.
Reviewed-by: Jose Fonseca <[email protected]>
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So that there are at most (2^22 * 6) texels, lower than the 2^26 limit.
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Initialize all 4 channels of undefined registers (that is, TEMPs that are used
before being assigned) in FS.
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The PRM specifies several padding requirements that we failed to honor.
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Not needed with do_dead_builtin_varyings.
Reviewed-by: Ian Romanick <[email protected]>
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Use variables that are easier to remember what they are.
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We can derive it from enabled_mask.
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Add loops that will be optimized away.
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