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* gallium: allow setting of the internal stream output offsetZack Rusin2014-03-071-2/+6
| | | | | | | | | | | | | | | | D3D10 allows setting of the internal offset of a buffer, which is in general only incremented via actual stream output writes. By allowing setting of the internal offset draw_auto is capable of rendering from buffers which have not been actually streamed out to. Our interface didn't allow. This change functionally shouldn't make any difference to OpenGL where instead of an append_bitmask you just get a real array where -1 means append (like in D3D) and 0 means do not append. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ilo: add support for PIPE_QUERY_PIPELINE_STATISTICSChia-I Wu2014-03-104-3/+108
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* ilo: add ILO_3D_PIPELINE_WRITE_STATISTICSChia-I Wu2014-03-105-0/+90
| | | | The command writes statistics registers to the specified bo.
* ilo: add some MI commands to GPEChia-I Wu2014-03-104-0/+116
| | | | We will need MI commands that load/store registers.
* ilo: set PIPE_CONTROL_GLOBAL_GTT_WRITE automaticallyChia-I Wu2014-03-102-2/+16
| | | | | Set the flag automatically in gen6_emit_PIPE_CONTROL(), and set it only for GEN6.
* ilo: print a warning when PPGTT is disabledChia-I Wu2014-03-102-0/+20
| | | | | Despite what the PRMs say, the driver appears to work fine when PPGTT is disabled. But at least print a warning in that case.
* ilo: require hardware logical context supportChia-I Wu2014-03-105-12/+12
| | | | The code paths are not tested for a while, and have some known issues.
* ilo: move ring types to winsysChia-I Wu2014-03-106-34/+11
| | | | | It results in less code despite that i915_drm.h specifies the ring type as part of the execution flags.
* ilo: winsys may limit the batch buffer sizeChia-I Wu2014-03-105-4/+12
| | | | | | The maximum batch buffer size is determined at the time of drm_intel_bufmgr_gem_init(). Make sure the pipe driver does not exceed the limit.
* ilo: PIPE_CAP_QUERY_TIMESTAMP may not be supportedChia-I Wu2014-03-102-1/+4
| | | | Reading TIMESTAMP register may fail, depending on both kernel and hardware.
* ilo: rework winsys batch buffer functionsChia-I Wu2014-03-103-16/+11
| | | | | | | | | | | Rename intel_winsys_check_aperture_size() to intel_winsys_can_submit_bo(), intel_bo_exec() to intel_winsys_submit_bo(), and intel_winsys_decode_commands() to intel_winsys_decode_bo(). Make a semantic change to ignore intel_context when the ring is not the render ring.
* ilo: replace bo alloc flags by initial domainsChia-I Wu2014-03-106-14/+16
| | | | | | The only alloc flag is INTEL_ALLOC_FOR_RENDER, which can as well be expressed by specifying the initial write domain. The change makes it obvious that we failed to set INTEL_ALLOC_FOR_RENDER in several places.
* ilo: remove intel_bo_get_size()Chia-I Wu2014-03-102-14/+18
| | | | | | Commit bfa8d21759c5f2b5b0885c696842167bd4c64fee uses it to work around a hardware limitation. But there are other ways to do it without the need for intel_bo_get_size().
* ilo: remove intel_bo_get_virtual()Chia-I Wu2014-03-104-90/+105
| | | | Make the map functions return the pointer directly.
* ilo: rework winsys bo reloc functionsChia-I Wu2014-03-104-8/+13
| | | | | | | | | | | | | Rename intel_bo_emit_reloc() to intel_bo_add_reloc(), intel_bo_clear_relocs() to intel_bo_truncate_relocs(), and intel_bo_references() to intel_bo_has_reloc(). Besides, we need intel_bo_get_offset() only to get the presumed offset afer adding a reloc entry. Remove the function and make intel_bo_add_reloc() return the presumed offset. While at it, switch to gem_bo->offset64 from gem_bo->offset.
* ilo: remove intel_winsys_enable_reuse()Chia-I Wu2014-03-101-2/+0
| | | | It should be an (winsys) implementation detail.
* gallium: rename R4A4 and A4R4 formats to match their swizzleMarek Olšák2014-03-071-1/+1
| | | | | | Like L4A4. Reviewed-by: Brian Paul <[email protected]>
* ilo: create u_upload_mgr lastChia-I Wu2014-02-261-8/+11
| | | | | Similar to u_blitter, u_upload_mgr is now a client of the pipe context. Its creation needs to be delayed until the context has been (almost) initialized.
* gallium: the other drivers don't support ARB_buffer_storageMarek Olšák2014-02-251-0/+1
| | | | Reviewed-by: Fredrik Höglund <[email protected]>
* gallium: add texture gather support to gallium (v3)Dave Airlie2014-02-251-0/+2
| | | | | | | | | | | | | | | | | | | | | This adds support to gallium for a TG4 instruction, and two CAPs. The first CAP is required for GL_ARB_texture_gather. The second CAP is required to expose GL_ARB_gpu_shader5. However so far we haven't found any hardware that natively exposes the textureGatherOffsets feature from GL, so just lower it for now. If hardware appears for this we can add another CAP to allow TG4 to take 4 offsets. v2: add component selection src and a cap to say hw can do it. (st can use to help control GL_ARB_gpu_shader5/GLSL 4.00). Add docs. v3: rename to SM5, add docs. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ilo: fix and enable fast depth clearChia-I Wu2014-02-222-9/+38
| | | | | | | | Use tex->bo_format instead of zs->format in ilo_blitter_rectlist_clear_zs() because the latter may be combined depth/stencil format. hiz_can_clear_zs() is no-op for GEN7+, but move the GEN check so that the assertions are tested. Finally, call the fast depth clear function from ilo_clear().
* ilo: add slice clear valueChia-I Wu2014-02-225-7/+78
| | | | | It is needed for 3DSTATE_CLEAR_PARAMS, and can also be used to track what value the slice has been cleared to.
* ilo: better readability and doc for texture flagsChia-I Wu2014-02-223-36/+58
| | | | | Improve comments for the flags, and explicitly separate their uses in slice flags and resolve flags.
* ilo: fix for stencil only rectlist opsChia-I Wu2014-02-222-2/+8
| | | | | 3DSTATE_STENCIL_BUFFER inherits some states from 3DSTATE_DEPTH_BUFFER. We need to emit both even the surface is stencil only.
* ilo: fix a false assertion failure on GEN6Chia-I Wu2014-02-221-4/+12
| | | | Layer offsetting is possible when it is level 0, layer 0.
* ilo: pipe_texture::usage is not a bitfieldChia-I Wu2014-02-221-1/+1
| | | | It happens to work because PIPE_USAGE_STAGING is 0x100.
* ilo: set ILO_TEXTURE_CPU_WRITE for imported texturesChia-I Wu2014-02-221-3/+10
| | | | | Assume the bo has been written by another process, which will trigger a HiZ resolve.
* gallium: add geometry shader output limitsGrigori Goronzy2014-02-091-0/+3
| | | | | | | | v2: adjust limits for radeonsi and llvmpipe v3: add documentation Cc: "10.1" <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium: remove PIPE_CAP_MAX_COMBINED_SAMPLERSMarek Olšák2014-02-041-2/+0
| | | | | | | This can be derived from the shader caps. All GPUs from ATI/AMD, NVIDIA, and INTEL have separate texture slots for each shader stage.
* ilo: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64Siavash Eliasi2014-01-291-1/+1
| | | | | | | | | | Ian manually ran the map_buffer_range* tests and the arb_map_buffer_alignment-* tests, but he did not do a full piglit run. v2 (idr): Use 64 instead of 4096 Tested-by: Ian Romanick <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* gallium: remove PIPE_CAP_SCALED_RESOLVEMarek Olšák2014-01-231-1/+0
| | | | | | | If any driver doesn't support this, it can use a blit after resolving the samples. Reviewed-by: Brian Paul <[email protected]>
* s/Tungsten Graphics/VMware/José Fonseca2014-01-173-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/[email protected]/[email protected]/ s/[email protected]/[email protected]/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\[email protected]/[email protected]/g s/keithw\[email protected]/[email protected]/g s/[email protected]/[email protected]/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/[email protected]/[email protected]/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <[email protected]>
* ilo: handle NULL renderbuffers correctlyChia-I Wu2014-01-146-27/+45
| | | | Renderbuffers may be NULL since 9baa45f78b8ca7d66280e36009b6a685055d7cd6.
* ilo: disable HiZ for misaligned levelsChia-I Wu2014-01-144-82/+215
| | | | | | | | | | | | | | We need to disable HiZ for non-8x4 aligned levels, except for level 0, layer 0. For the very first layer we can adjust Width and Height fields of 3DSTATE_DEPTH_BUFFER to make it aligned. Specifically, add ILO_TEXTURE_HIZ and set the flag only for properly aligned levels. ilo_texture_can_enable_hiz() is updated to check for the flag. In tex_layout_validate(), align the depth bo to 8x4 so that we can adjust Width/Height of 3DSTATE_DEPTH_BUFFER without introducing out-of-bound access. Finally in rectlist blitter, add the ability to adjust 3DSTATE_DEPTH_BUFFER.
* ilo: use a helper to determine if HiZ is enabledChia-I Wu2014-01-145-8/+19
| | | | | Add ilo_texture_can_enable_hiz and replace all checks for tex->hiz.bo by calls to ilo_texture_can_enable_hiz().
* ilo: decide on hiz first in texture allocationChia-I Wu2014-01-141-64/+64
| | | | | | | | | Add tex_layout_init_hiz() before tex_layout_init_format() to decide whether HiZ should be enabled. On GEN6, because of layer offsetting, HiZ is enabled only when the texture is non-mipmapped and non-array. PIPE_USAGE_STAGING is also taken as a hint to disable HiZ.
* ilo: emit gen7_wa_pipe_control_wm_max_threads_stall on HaswellChia-I Wu2014-01-141-7/+9
| | | | | | | Rename the workaround, as it is for 3DSTATE_PS instead of 3DSTATE_WM, and emit it on Haswell too. This does not fix any app, but an assertion failure.
* ilo: use HALIGN_4 on GEN7 for depth buffersChia-I Wu2014-01-141-11/+1
| | | | The comment was no longer true since 6642381e7513926b847d6bc10bf590e1c0c54859.
* ilo: OOM for HiZ is fatal on GEN6Chia-I Wu2014-01-141-2/+7
| | | | On GEN6, HiZ and Separate Stencil Buffer must be enabled at the same time.
* ilo: fix a HiZ bo leakageChia-I Wu2014-01-141-0/+3
| | | | Dereference the HiZ bo when the texture is destroyed.
* ilo: simplify ilo_texture_set_slice_flags()Chia-I Wu2014-01-141-5/+3
| | | | | Call ilo_texture_get_slice() for the last slice so that we can get rid of the duplicated assert().
* ilo: enable HiZChia-I Wu2014-01-084-7/+45
| | | | | | The support is still early. Fast depth buffer clear is not enabled yet. HiZ can be forced off with ILO_DEBUG=nohiz.
* ilo: resolve Z/HiZ correctlyChia-I Wu2014-01-085-1/+234
| | | | | | When the depth buffer is to be read, perform a Depth Buffer Resolve if it has been rendered. When the depth buffer is to be rendered, perform a HiZ Buffer Resolve when the depth buffer is modified externally.
* ilo: add flags to texture slicesChia-I Wu2014-01-081-0/+29
| | | | | The flags are used to mark who (CPU, BLT, or RENDER) has accessed the resource and how (READ or WRITE).
* ilo: rename and add an accessor for texture slicesChia-I Wu2014-01-084-19/+41
| | | | | Rename ilo_texture::slice_offsets to ilo_texture::slices and add an accessor, ilo_texture_get_slice().
* ilo: add HiZ op support to the pipelinesChia-I Wu2014-01-0811-4/+1070
| | | | | | Add blitter functions to perform Depth Buffer Clear, Depth Buffer Resolve, and Hierarchical Depth Buffer Resolve. Those functions set ilo_blitter up and pass it to the pipelines to emit the commands.
* ilo: add support for HiZ allocationChia-I Wu2014-01-082-1/+82
| | | | Add tex_create_hiz() to create HiZ bo. It is not really called yet.
* ilo: refactor separate stencil allocationChia-I Wu2014-01-081-20/+27
| | | | | Move separate stencil allocation code to tex_create_separate_stencil to keep tex_create sane.
* ilo: assorted GPE fixes for HiZChia-I Wu2014-01-085-69/+67
| | | | | | | Allow HiZ op to be specified in 3DSTATE_WM. Pass depth format directly in gen7_emit_3DSTATE_SF. Use tex->hiz.bo to determine if HiZ exists. Fix 3DSTATE_SF for the case when there is no ilo_rasterizer_state. Fix 3DSTATE_PS for the case when there is no ilo_shader_state.
* ilo: no layer offsetting on GEN7+Chia-I Wu2014-01-081-1/+5
| | | | | Even though the Ivy Bridge PRM lists some restrictions that require layer offsetting as the Sandy Bridge PRM does, it seems they are actually lifted.
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