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* ilo: clarify valid and preferred tilingsChia-I Wu2015-03-072-15/+29
| | | | | We did it right until the switch to gen_surface_tiling, which has GEN8_TILING_W. Generally, GEN8_TILING_W may be valid but not preferred.
* ilo: clean up Gen6 WAsChia-I Wu2015-03-071-34/+62
| | | | | | Add a help function for each WA and make PIPE_CONTROL flags match the WA descriptions. Call gen6_wa_pre_pipe_contro() only before PIPE_CONTROLs. Fix missing gen6_wa_pre_3dstate_vs_toggle() in the rectlist path.
* ilo: add generic ilo_render_3dprimitive()Chia-I Wu2015-03-074-53/+29
| | | | It replaces gen[6-8]_3dprimitive().
* ilo: add generic ilo_render_pipe_control()Chia-I Wu2015-03-075-101/+56
| | | | | It replaces gen[6-8]_pipe_control() and a direct gen6_PIPE_CONTROL() call in ilo_render_emit_flush().
* ilo: fix padding of linear sampler viewsChia-I Wu2015-03-071-4/+2
| | | | Should use the temporary variable in the loop instead of layout->bo_height.
* ilo: do not check for interleaved_samplesChia-I Wu2015-03-071-2/+1
| | | | | interleaved_samples is only zero-initialized when layout_want_mcs() is called. We should not check for it. There is also no need to.
* ilo: enable L3 cache in MOCSChia-I Wu2015-03-065-17/+85
| | | | This enables L3 cache in MOCS almost everywhere.
* ilo: track if a ilo_view_surface is a scanoutChia-I Wu2015-03-062-16/+16
| | | | Scanouts require a different cache type.
* ilo: clean up SURFACE_STATE and BINDING_TABLE_STATEChia-I Wu2015-03-062-21/+35
| | | | | Add ilo_builder_surface_pointer() to replace ilo_builder_surface_write(). Make Gen8+ take a different path in gen6_SURFACE_STATE().
* ilo: add more convenient intel_bo_{ref,unref}()Chia-I Wu2015-03-067-42/+26
| | | | | They both check for NULL and intel_bo_ref() returns the referenced bo. They replace intel_bo_{reference,unreference}().
* ilo: add intel_bo_set_tiling()Chia-I Wu2015-03-065-41/+38
| | | | | Make intel_winsys_alloc_bo() always allocate a linear bo, and add intel_bo_set_tiling() to set the tiling. Document the purpose of tiling.
* ilo: replace intel_tiling_mode by gen_surface_tilingChia-I Wu2015-03-0610-136/+167
| | | | | | The former is used by the kernel driver to set up fence registers and to pass tiling info across processes. It lacks INTEL_TILING_W, which made our code less expressive.
* ilo: update genhw headersChia-I Wu2015-03-067-782/+986
| | | | The main change is non-inline <enum>s are now generated as C enums.
* ilo: improve WA handling in rectlist pathChia-I Wu2015-03-044-38/+60
| | | | | | Add wrappers for 3DPRIMITIVE to make sure we clear current_pipe_control_dw1 and deferred_pipe_control_dw1 after it. Add missing gen7_wa_post_ps_and_later().
* ilo: clean up Gen7.5 WAsChia-I Wu2015-03-042-51/+43
| | | | | | | | | | | | These WAs gen7_wa_post_3dstate_push_constant_alloc_ps() gen7_wa_pre_vs() gen7_wa_pre_3dstate_sf_depth_bias() first half of gen7_wa_pre_depth() gen7_wa_post_ps_and_later() are Gen7-specific. Update copy-and-pasted gen8_wa_pre_depth() also.
* ilo: add ILO_DEBUG=hangChia-I Wu2015-03-055-4/+45
| | | | When set, detect and dump the hanging batch bufffer.
* ilo: add some more winsys functionsChia-I Wu2015-03-041-1/+29
| | | | | | Add intel_winsys_get_reset_stats(), intel_winsys_import_userptr(), and intel_bo_map_async(). The latter two are stubs, but we are not going to use them immediately either.
* ilo: R32G32B32_FLOAT need no special care on Gen8+Chia-I Wu2015-02-211-3/+6
| | | | | Gen8+ must use VALIGN_4. Unlike prior Gens, R32G32B32_FLOAT should supposedly support VALIGN_4.
* ilo: 128 BPP formats can use TiledY on Gen7.5+Chia-I Wu2015-02-211-1/+6
| | | | The restriction is lifted.
* ilo: fix PCB alloc asserts on Gen7.5 GT3Chia-I Wu2015-02-181-1/+5
| | | | GT3 has two slices and all limits are doubled.
* ilo: fix compiler warningsChia-I Wu2015-02-183-8/+12
| | | | | Fix -Wmaybe-uninitialized warnings. The change to ilo_blit_resolve_slices_for_hiz() is a potential bug fix.
* gallium: add interface and state tracker support for GL_AMD_pinned_memoryMarek Olšák2015-02-171-0/+1
| | | | | | v2: add alignment restrictions to docs, fix indentation in headers Reviewed-by: Christian König <[email protected]>
* ilo: always set up BLEND_STATE on Gen8Chia-I Wu2015-02-171-7/+1
| | | | There is now an DW0 that seems to be always referenced.
* ilo: fix alpha test on Gen8Chia-I Wu2015-02-171-5/+26
| | | | | Shoudl use GEN8_BLEND_DW0_ALPHA_TEST_ENABLE instead of GEN6_RT_DW1_ALPHA_TEST_ENABLE (and others).
* ilo: fix some state pointer commands on Gen8Chia-I Wu2015-02-151-0/+20
| | | | | | 3DSTATE_CC_STATE_POINTERS seems to be ignored when bit 0 of DW1 is not set. Follow i965 and set the bit for 3DSTATE_CC_STATE_POINTERS and 3DSTATE_BLEND_STATE_POINTERS. Add gen checks for all state pointer commands.
* ilo: fix JIP/UIP on Gen8Chia-I Wu2015-02-142-9/+25
| | | | UIP is in DW2 and JIP is in DW3 on Gen8. Also, the units are in bytes.
* ilo: do not set GEN6_THREADCTRL_SWITCHChia-I Wu2015-02-141-4/+0
| | | | It is not needed on Gen6+, and it appears to be broken on Gen8.
* ilo: correct ISA UIP/JIP decoding for Gen8Chia-I Wu2015-02-141-18/+39
| | | | JIP is int32_t and UIP is in DW2 on Gen8.
* ilo: prepare for 64-bit immediates decodingChia-I Wu2015-02-141-15/+31
| | | | Replace imm32 by imm64. Add more ways (UD, D, etc) to access the immediate.
* ilo: cleanup ISA DW1 decodingChia-I Wu2015-02-141-34/+55
| | | | Decode the higher and lower 16 bits separately.
* ilo: cleanup ISA DW0 decodingChia-I Wu2015-02-141-10/+16
| | | | | Add disasm_inst_decode_dw0_opcode_gen6() to decode the opcode. Simplify branch_ctrl/acc_wr_ctrl decoding.
* ilo: update some outdated gen checksChia-I Wu2015-02-141-4/+4
| | | | | | Update gen checks for 3DSTATE_POLY_STIPPLE_OFFSET, 3DSTATE_POLY_STIPPLE_PATTERN, 3DSTATE_LINE_STIPPLE, and 3DSTATE_AA_LINE_PARAMETERS.
* ilo: fix rectlist length on Gen8Chia-I Wu2015-02-141-1/+1
| | | | 5 PIPE_CONTROLs, 2 3DSTATE_WM_HZ_OP, and depth buffer setup require 65 DWords.
* ilo: fix 3DSTATE_VF_TOPOLOGYChia-I Wu2015-02-141-2/+1
| | | | The pipe primitive type was wrongly translated twice.
* ilo: update screen init for Gen8Chia-I Wu2015-02-121-8/+32
| | | | | This is very preliminary and is only tested with glxgears. All information about Gen8 is derived from i965 and beignet.
* ilo: update outdated render command emissions for Gen8Chia-I Wu2015-02-121-4/+4
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* ilo: update rectlist command emission for Gen8Chia-I Wu2015-02-124-7/+93
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* ilo: update draw command emission for Gen8Chia-I Wu2015-02-126-34/+517
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* ilo: update surface state emission for Gen8Chia-I Wu2015-02-121-7/+8
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* ilo: update dynamic state emission for Gen8Chia-I Wu2015-02-121-14/+26
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* ilo: update outdated gen assertions for Gen8Chia-I Wu2015-02-126-24/+23
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* ilo: add new WM related helpers for Gen8Chia-I Wu2015-02-121-0/+76
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* ilo: update VS related functions for Gen8Chia-I Wu2015-02-122-1/+31
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* ilo: update VF related functions for Gen8Chia-I Wu2015-02-122-42/+157
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* ilo: update SAMPLER_STATE for Gen8Chia-I Wu2015-02-121-29/+42
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* ilo: update SAMPLER_BORDER_COLOR_STATE for Gen8Chia-I Wu2015-02-121-2/+3
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* ilo: update depth clear value for Gen8Chia-I Wu2015-02-121-1/+4
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* ilo: update ilo_zs_surface for Gen8Chia-I Wu2015-02-125-82/+137
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* ilo: update ilo_view_surface for Gen8Chia-I Wu2015-02-124-43/+141
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* ilo: update texture layout for Gen8Chia-I Wu2015-02-121-1/+3
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