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path: root/src/gallium/drivers/ilo/ilo_resource.c
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* ilo: replace bo alloc flags by initial domainsChia-I Wu2014-03-101-8/+11
| | | | | | The only alloc flag is INTEL_ALLOC_FOR_RENDER, which can as well be expressed by specifying the initial write domain. The change makes it obvious that we failed to set INTEL_ALLOC_FOR_RENDER in several places.
* ilo: remove intel_bo_get_size()Chia-I Wu2014-03-101-0/+17
| | | | | | Commit bfa8d21759c5f2b5b0885c696842167bd4c64fee uses it to work around a hardware limitation. But there are other ways to do it without the need for intel_bo_get_size().
* ilo: pipe_texture::usage is not a bitfieldChia-I Wu2014-02-221-1/+1
| | | | It happens to work because PIPE_USAGE_STAGING is 0x100.
* ilo: set ILO_TEXTURE_CPU_WRITE for imported texturesChia-I Wu2014-02-221-3/+10
| | | | | Assume the bo has been written by another process, which will trigger a HiZ resolve.
* ilo: disable HiZ for misaligned levelsChia-I Wu2014-01-141-5/+80
| | | | | | | | | | | | | | We need to disable HiZ for non-8x4 aligned levels, except for level 0, layer 0. For the very first layer we can adjust Width and Height fields of 3DSTATE_DEPTH_BUFFER to make it aligned. Specifically, add ILO_TEXTURE_HIZ and set the flag only for properly aligned levels. ilo_texture_can_enable_hiz() is updated to check for the flag. In tex_layout_validate(), align the depth bo to 8x4 so that we can adjust Width/Height of 3DSTATE_DEPTH_BUFFER without introducing out-of-bound access. Finally in rectlist blitter, add the ability to adjust 3DSTATE_DEPTH_BUFFER.
* ilo: decide on hiz first in texture allocationChia-I Wu2014-01-141-64/+64
| | | | | | | | | Add tex_layout_init_hiz() before tex_layout_init_format() to decide whether HiZ should be enabled. On GEN6, because of layer offsetting, HiZ is enabled only when the texture is non-mipmapped and non-array. PIPE_USAGE_STAGING is also taken as a hint to disable HiZ.
* ilo: use HALIGN_4 on GEN7 for depth buffersChia-I Wu2014-01-141-11/+1
| | | | The comment was no longer true since 6642381e7513926b847d6bc10bf590e1c0c54859.
* ilo: OOM for HiZ is fatal on GEN6Chia-I Wu2014-01-141-2/+7
| | | | On GEN6, HiZ and Separate Stencil Buffer must be enabled at the same time.
* ilo: fix a HiZ bo leakageChia-I Wu2014-01-141-0/+3
| | | | Dereference the HiZ bo when the texture is destroyed.
* ilo: enable HiZChia-I Wu2014-01-081-7/+41
| | | | | | The support is still early. Fast depth buffer clear is not enabled yet. HiZ can be forced off with ILO_DEBUG=nohiz.
* ilo: rename and add an accessor for texture slicesChia-I Wu2014-01-081-7/+9
| | | | | Rename ilo_texture::slice_offsets to ilo_texture::slices and add an accessor, ilo_texture_get_slice().
* ilo: add support for HiZ allocationChia-I Wu2014-01-081-1/+77
| | | | Add tex_create_hiz() to create HiZ bo. It is not really called yet.
* ilo: refactor separate stencil allocationChia-I Wu2014-01-081-20/+27
| | | | | Move separate stencil allocation code to tex_create_separate_stencil to keep tex_create sane.
* gallium, intel: Implements new __DRI_IMAGE_USE_LINEAR and PIPE_BIND_LINEAR ↵Axel Davy2013-09-061-1/+1
| | | | | | flags to enforce no tiling. Signed-off-by: Axel Davy <[email protected]>
* ilo: honor surface padding requirementsChia-I Wu2013-07-101-0/+53
| | | | The PRM specifies several padding requirements that we failed to honor.
* ilo: update winsys interfaceChia-I Wu2013-06-121-7/+14
| | | | | | The motivation is to kill tiling and pitch in struct intel_bo. That requires us to make tiling and pitch not queryable, and be passed around as function parameters.
* ilo: get rid of function tables in winsysChia-I Wu2013-06-121-12/+10
| | | | | We are moving toward making struct intel_bo alias drm_intel_bo. As a first step, we cannot have function tables.
* ilo: remove unnecessary tex_set_bo/buf_set_boChia-I Wu2013-06-121-42/+18
| | | | Merge the bodies to tex_create_bo/buf_create_bo respectively.
* ilo: add support for stencil resources on GEN7+Chia-I Wu2013-05-161-1/+49
| | | | | | For allocations, we need to support stencil-only and separate stencil resources. For mapping, we need to support software tiling and packing/unpacking for separate stencil resources.
* ilo: simplify ilo_texture_get_slice_offset()Chia-I Wu2013-05-151-51/+36
| | | | Always return a tile-aligned offset. Also fix for W tiling.
* ilo: rework ilo_textureChia-I Wu2013-05-141-541/+730
| | | | | Use ilo_buffer for buffer resources and ilo_texture for texture resources. A major cleanup is necessitated by the separation.
* ilo: rename ilo_resource to ilo_textureChia-I Wu2013-05-141-154/+154
| | | | In preparation for the introduction of ilo_buffer.
* ilo: move transfer-related functions to a new fileChia-I Wu2013-05-141-447/+3
| | | | | | Resource mapping is distinct from resource allocation, and is going to get more and more complex. Move the related functions to a new file to make the separation clear.
* ilo: Initialize read_back in transfer_map_sys.Vinson Lee2013-05-101-1/+1
| | | | | | | Fixes "Uninitialized scalar variable" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* ilo: add support for PIPE_FORMAT_ETC1_RGB8Chia-I Wu2013-05-091-5/+56
| | | | It is decompressed to and stored as PIPE_FORMAT_R8G8B8X8_UNORM on-the-fly.
* ilo: support mapping with a staging system bufferChia-I Wu2013-05-091-0/+77
| | | | | It can be used for unpacking compressed texture on-the-fly or to support explicit transfer flushing.
* ilo: allow for different mapping methodsChia-I Wu2013-05-091-115/+187
| | | | | We want to or need to use a different mapping method when when the resource is busy, the bo format differs from the requested format, and etc.
* ilo: allow bo format to differ from that requestedChia-I Wu2013-05-091-14/+21
| | | | | For separate stencil buffer or formats not supported natively, the real format of the bo may differ from that requested.
* ilo: fix tiling/size for special-purpose resourcesChia-I Wu2013-05-011-2/+30
| | | | We do not allocate such resources yet though.
* ilo: use UMS layout for render targetsChia-I Wu2013-05-011-19/+99
| | | | | As we do not advertise MSAA support, this change should not make any difference yet.
* ilo: support and prefer compact array spacingChia-I Wu2013-05-011-13/+64
| | | | | There is no reason to waste the memory when the HW can support compact array spacing (ARYSPC_LOD0).
* ilo: add ilo_dev_info shared by the screen and contextsChia-I Wu2013-05-011-5/+5
| | | | | The struct is used to describe the device information, such as PCI ID, GEN, GT, and etc.
* ilo: add GEN6 GPEChia-I Wu2013-04-261-0/+98
| | | | | GEN6 GPE (Graphics Processing Engine) is a low-level interface to emit 3D commands and states.
* ilo: hook up pipe context transfer functionsChia-I Wu2013-04-261-4/+239
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* ilo: hook up pipe screen resource functionsChia-I Wu2013-04-261-5/+810
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* ilo: new pipe driver for Intel GEN6+Chia-I Wu2013-04-261-0/+55
This commit adds some boilerplate code. The header files found under include/ are copied from i965.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 18:45:39 +0000