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* gallium: Add a pipe cap for whether primitive restart works for patches.Kenneth Graunke2016-05-231-0/+1
| | | | | | | | | | | | | | | Some hardware supports primitive restart on patch primitives, and other hardware does not. Modern GL and ES include a query for this feature; adding a capability bit will allow us to answer it. As far as I know, AMD hardware does not support this feature, while NVIDIA and Intel hardware does. However, most Gallium drivers do not appear to support tessellation shaders yet. So, I've enabled it for nvc0 and disabled it everywhere else. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/ir3: disable cp for indirect src'sRob Clark2016-05-231-0/+9
| | | | | | | | | | | | The variable-indexing tests always had a few random fails, which I usually couldn't reproduce when running tests manually. Somehow recently this got a lot worse. I ported a couple of the shaders to GLES to see what blob does, and it also seems to be avoiding to cp indirect srcs. So I guess indirect w/ instructions other than cat1 (mov) are not totally reliable. Let's just switch that off until this is better understood. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: need to lower fmod tooRob Clark2016-05-201-0/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix compiler warningRob Clark2016-05-171-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: small standalone compiler cleanupRob Clark2016-05-151-2/+1
| | | | | | Don't hard-code the gpu-id anymore. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: lower fdivRob Clark2016-05-151-0/+1
| | | | | | | Not sure how we didn't hit this already, but since we want fdiv converted into mul + rcp, we should set this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle VARYING_SLOT_PNTCRob Clark2016-05-151-0/+12
| | | | | | | In the glsl->tgsi path, this already gets translated to VAR8, which matches up with rasterizer->sprite_coord_enable. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: disable TGSI specific hacks in nir caseRob Clark2016-05-154-2/+7
| | | | | | | When we got NIR directly from state tracker (vs using tgsi_to_nir) we need to realize this and skip some TGSI specific hacks. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add support for NIR as preferred IRRob Clark2016-05-156-18/+61
| | | | | | For now under debug flag, since only suitable for debugging/testing. Signed-off-by: Rob Clark <[email protected]>
* gallium: Add a pipe cap for arb_cull_distanceTobias Klausmann2016-05-141-0/+1
| | | | | | | | | This lets us safely enable or disable the extension as needed Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nir/algebraic: Separate ffma lowering from fusingJason Ekstrand2016-05-111-0/+1
| | | | | | | | The i965 driver has its own pass for fusing mul+add combinations that's much smarter than what nir_opt_algebraic can do so we don't want to get the nir_opt_algebraic one just because we didn't set lower_ffma. Reviewed-by: Kenneth Graunke <[email protected]>
* freedreno: fix multi-layer transfer_map'sRob Clark2016-05-111-1/+1
| | | | | | | | The use of transfer_inline_write() in TexSubImage path (see fb9fe352ea4) exposed a bug for "layer_first" resources (ie. a4xx) not setting correct layer_stride. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: size input/output arrays properlyRob Clark2016-05-101-3/+14
| | | | | | | | | We index into these based on var->data.driver_location, which might have gaps (ie. two inputs, one w/ drvloc 0 and other 2). This shows up in (for example) 'bin/copyteximage 1D', but was only noticed recently due to additional asserts. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: lower lrp when operating with double operandsSamuel Iglesias Gonsálvez2016-05-101-0/+1
| | | | | | | | | Lower lrp when operating with double operands because float version of lrp is also lowered. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* freedreno/ir3: fix fallout from new block iteratorsRob Clark2016-05-091-1/+1
| | | | | | | Since this is potentially modifying the block structure of the shader, it needs the _safe() version of the iterator. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: allow for additional VS sysval inputsRob Clark2016-05-091-2/+5
| | | | | | | | | | | | There are a total of four possible currently, rather than 2. So we need to be prepared for the input array to grow by 16 components. We could get away with less if we could pack sysval inputs.. and the way this is handled currently isn't really the nicest thing. But it's a tactical fix for an issue hit in: GL31-CTS.gtf30.GL3Tests.transform_feedback.transform_feedback_vertex_id Signed-off-by: Rob Clark <[email protected]>
* ir3: fixup for new nir_foreach_block()Connor Abbott2016-05-051-30/+21
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* freedreno: remove null check before freeThomas Hindoe Paaboel Andersen2016-05-051-2/+1
| | | | Reviewed-by: Eduardo Lima Mitev <[email protected]>
* freedreno: allow ctx->draw_vbo to failRob Clark2016-05-045-30/+37
| | | | | | | Pretty much only happens if shader variant compile fails. But in this case, if we haven't emitted cmdstream, we don't want to set needs_flush. Signed-off-by: Rob Clark <[email protected]>
* freedreno: move shader-stage dirty bits to global dirty flagRob Clark2016-05-048-59/+41
| | | | | | | | | | | This was always a bit overly complicated, and had some issues (like ctx->prog.dirty not getting reset at the end of the batch). It also required some special hacks to avoid resetting dirty state on binning pass. So just move it all into ctx->dirty (leaving some free bits for future shader stages), and make FD_DIRTY_PROG just be the union of all FD_SHADER_DIRTY_*. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fix bogus offset for f32x24s8 stencil restoreRob Clark2016-05-041-4/+5
| | | | | | fixes: $piglit/bin/fbo-clear-formats GL_ARB_depth_buffer_float Signed-off-by: Rob Clark <[email protected]>
* freedreno: add some debug_asserts() to catch insane offsetsRob Clark2016-05-041-0/+2
| | | | | | | Ofc won't catch *all* faults, but at least helpful for catching offsets which are completely bogus. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: deal with VS which do not write positionRob Clark2016-05-041-0/+7
| | | | | | | | Fixes $piglit/bin/glsl-1.40-tf-no-position a3xx may need similar? Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove a couple redundant is_flow()sRob Clark2016-05-042-2/+2
| | | | | | | Now that the opc's encode the instruction category (making them unique) we no longer need to check the category in addition to the opc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cp small negative integers tooRob Clark2016-05-041-1/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix # of registersRob Clark2016-05-041-1/+1
| | | | | | | The instruction encoding allows for more registers, but at least on a3xx/a4xx they don't actually exist. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: lower immeds to constRob Clark2016-05-043-4/+80
| | | | | | | | | | | | | | | | | Helps reduce register pressure and instruction counts for immediates that would otherwise require a mov into gpr. total instructions in shared programs: 4455332 -> 4369297 (-1.93%) total dwords in shared programs: 8807872 -> 8614432 (-2.20%) total full registers used in shared programs: 263062 -> 250846 (-4.64%) total half registers used in shader programs: 9845 -> 9845 (0.00%) total const registers used in shared programs: 1029735 -> 1466993 (42.46%) half full const instr dwords helped 0 10415 0 17861 5912 hurt 0 1157 21458 947 33 Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add ir3_cp_ctxRob Clark2016-05-043-12/+22
| | | | | | Needed in next commit.. just split out to reduce noise. Signed-off-by: Rob Clark <[email protected]>
* freedreno: s/Elements/ARRAY_SIZE/Brian Paul2016-05-031-1/+1
| | | | | Signed-off-by: Brian Paul <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/ir3: use pipe_debug_callback for shader-db tracesRob Clark2016-04-306-33/+43
| | | | | | For multi-threaded shader-db support. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add debug callback to emitRob Clark2016-04-303-0/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add debug callback to emitRob Clark2016-04-303-0/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: wire up core pipe_debug_callbackRob Clark2016-04-302-0/+15
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle color clamp variant ourselvesRob Clark2016-04-305-3/+28
| | | | | | | | | Now that there is a pass to do this in NIR, lets just use that and manage the variants ourself, rather than letting state-tracker do it. This way, mesa/st will precompile shaders without requiring ST_DEBUG=precompile (which requires a debug build). Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix indentationRob Clark2016-04-303-12/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* nir: Switch the arguments to nir_foreach_use and friendsJason Ekstrand2016-04-281-1/+1
| | | | | | | | | | | This matches the "foreach x in container" pattern found in many other programming languages. Generated by the following regular expression: s/nir_foreach_use(\([^,]*\),\s*\([^,]*\))/nir_foreach_use(\2, \1)/ and similar expressions for nir_foreach_use_safe, etc. Reviewed-by: Ian Romanick <[email protected]>
* nir: Switch the arguments to nir_foreach_functionJason Ekstrand2016-04-282-2/+2
| | | | | | | | | This matches the "foreach x in container" pattern found in many other programming languages. Generated by the following regular expression: s/nir_foreach_function(\([^,]*\),\s*\([^,]*\))/nir_foreach_function(\2, \1)/ Reviewed-by: Ian Romanick <[email protected]>
* nir: Switch the arguments to nir_foreach_phi_srcJason Ekstrand2016-04-281-1/+1
| | | | | | | | | | | This matches the "foreach x in container" pattern found in many other programming languages. Generated by the following regular expression: s/nir_foreach_phi_src(\([^,]*\),\s*\([^,]*\))/nir_foreach_phi_src(\2, \1)/ and a similar expression for nir_foreach_phi_src_safe. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir: Switch the arguments to nir_foreach_instrJason Ekstrand2016-04-282-4/+4
| | | | | | | | | | | This matches the "foreach x in container" pattern found in many other programming languages. Generated by the following regular expression: s/nir_foreach_instr(\([^,]*\),\s*\([^,]*\))/nir_foreach_instr(\2, \1)/ and similar expressions for nir_foreach_instr_safe etc. Reviewed-by: Ian Romanick <[email protected]>
* nir: rename lower_flrp to lower_flrp32Samuel Iglesias Gonsálvez2016-04-281-1/+1
| | | | | | | A later patch will add lower_flrp64 option to NIR. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* gallium: Remove every double semi-colonJakob Sinclair2016-04-261-1/+1
| | | | | | Signed-off-by: Jakob Sinclair <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* freedreno/a3xx: remove unused fxnRob Clark2016-04-251-6/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: convert over to rallocRob Clark2016-04-252-40/+6
| | | | | | | | | The home-grown heap scheme (which is ultra-simple but probably not good to always allocate and memset such a chunk of memory up front) was a remnant of fdre (where the ir originally came from). But since we have ralloc in mesa, lets just use that instead. Signed-off-by: Rob Clark <[email protected]>
* freedreno: honor handle->offsetRob Clark2016-04-251-2/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: disallow cat4 immed srcRob Clark2016-04-251-1/+1
| | | | | | | | Normally this would never happen (constant-propagation in NIR would eliminate the instruction), except it does happen for 'undef' which we turn into immed 0.0 for bookkeeping purposes. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add render-target formatsRob Clark2016-04-251-3/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2016-04-255-5/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: reduce line width for deqp furtherRob Clark2016-04-251-1/+1
| | | | | | | | See a7eb12d0.. but that wasn't restrictive enough. Fixes dEQP-GLES3.functional.rasterization.primitives.line_strip_wide, and similar Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix sin/cosRob Clark2016-04-258-1/+92
| | | | | | | | | | We seem to need range reduction to get sane results. Fixes glmark2 jellyfish bench, and a whole bunch of dEQP-GLES3.functional.shaders.builtin_functions.precision.{sin,cos,tan}.* v2: squashed in android build fixes from Rob Herring Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: relax restriction in groupingRob Clark2016-04-241-3/+5
| | | | | | | | | | Currently we were two restrictive, and would insert an output move in cases like: MOV OUT[0], IN[0].xyzw Loosen the restriction to allow the current instruction to appear in the neighbor list but only at it's current possition. Signed-off-by: Rob Clark <[email protected]>
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