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* freedreno: core SSBO supportRob Clark2017-05-045-0/+73
| | | | | | The generation-independent support for binding shader buffer objects. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: resync instr-a3xx.h/disasm-a3xx.cRob Clark2017-05-047-20/+161
| | | | | | | Sync to the same files from freedreno.git to correct decoding of ldgb/ stgb instructions. Signed-off-by: Rob Clark <[email protected]>
* gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERSSamuel Pitoiset2017-04-261-0/+1
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a5xx: hack for r8g8b8a8_snormRob Clark2017-04-231-1/+1
| | | | | | | | | Blob won't render to this format, and sampling from it it uses the same fmt value for r8g8b8_snorm and r8g8b8a8_snorm. But this is what is what blocks us from jumping from gl30/gles20 to gl31/gles30. So a hack it is! Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: rgtc formatsRob Clark2017-04-232-8/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: occlusion queryRob Clark2017-04-224-3/+140
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: drop ring arg from _set_stage()Rob Clark2017-04-227-17/+13
| | | | | | | | It is always the draw ring. Except for a5xx queries like time-elapsed, where we will eventually want to emit cmds into both binning and draw rings. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-04-226-12/+25
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add support for hw accumulating queriesRob Clark2017-04-228-33/+384
| | | | | | | | | | | | | Some queries on a4xx and all queries on a5xx can do result accumulation on CP so we don't need to track per-tile samples. We do still need to handle pausing/resuming while switching batches (in case the query is active over multiple draws which are executed out of order). So introduce new accumulated-query helpers for these sorts of queries, since it doesn't really fit in cleanly with the original query infra- structure. Signed-off-by: Rob Clark <[email protected]>
* freedreno: a bit of query refactorRob Clark2017-04-224-40/+40
| | | | | | | | Move a bit more of the logic shared by all query types (active tracking, etc) into common code. This avoids introducing a 3rd copy of that logic for a5xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: make hw-query a helperRob Clark2017-04-2213-16/+57
| | | | | | | | | For a5xx (and actually some queries on a4xx) we can accumulate results in the cmdstream, so we don't need this elaborate mechanism of tracking per-tile query results. So make it into vfuncs so generation specific backend can use it when it makes sense. Signed-off-by: Rob Clark <[email protected]>
* gallium: fold u_trim_pipe_prim call from st/mesa to driversMarek Olšák2017-04-201-0/+5
| | | | | | | Most drivers don't need it and shouldn't need it because it can't be used in some cases (indirect draws, primitive restart, count from streamout). Reviewed-by: Brian Paul <[email protected]>
* freedreno: refactor dirty state handlingRob Clark2017-04-1819-101/+119
| | | | | | | | In particular, move per-shader-stage info out to a seperate array of enum's indexed by shader stage. This will make it easier to add more shader stages as well as new per-stage state (like SSBOs). Signed-off-by: Rob Clark <[email protected]>
* freedreno: move clear path dirty state hack to a2xx backendRob Clark2017-04-182-9/+9
| | | | | | | | | a3xx/a4xx use the generic u_blitter path, which will make state dirty bits be set appropriately thanks to the automagic of generic code setting generic state in the driver. And a5xx has a blit/dma engine (actually, two) so it doesn't need these extra dirty bits set. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out per-stage emit_consts fxnsRob Clark2017-04-185-21/+41
| | | | | | | | | This makes it easier to deal with adding additional stages which have their own driver-params. The duplicated code this introduces can be refactored out after a later patch moves to per-shader-stage dirty flags. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add helper to mark all state cleanRob Clark2017-04-189-52/+34
| | | | | | | | Note that this involves juggling around a bit when we emit and clear texture state. So split out from the patch that adds the helper to set all state dirty. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add helper to mark all state dirtyRob Clark2017-04-184-6/+13
| | | | | | This will simplify things when we break out per-shader-stage dirty bits. Signed-off-by: Rob Clark <[email protected]>
* freedreno: move a2xx specific hack out of coreRob Clark2017-04-182-10/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: make texture state an arrayRob Clark2017-04-1810-39/+45
| | | | | | | | Make this an array indexed by shader stage, as is done elsewhere for other per-shader-stage state. This will simplify things as more shader stages are eventually added. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: refactor out helpers for comparing shader keysRob Clark2017-04-184-79/+63
| | | | | | | | | | | | Each of the ir3 users has *basically* the same logic for comparing the previous and current shader key, to see which, if any, shader state needs to be marked dirty due to shader variant change. The difference between gen's was just that some lowering flags never get set on certain generations. But it doesn't really hurt to include the extra checks (because both keys would have false). Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix crash if ctx torn down with no renderingRob Clark2017-04-171-1/+1
| | | | | | | | In this case, ctx->flush_queue would not have been initialized. Fixes: 0b613c20 ("freedreno: enable draw/batch reordering by default") Cc: "17.1" <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add 'high' register classRob Clark2017-04-173-67/+131
| | | | | | | | For compute shaders, we need to be able to allocate some "high" registers (r48.x to r55.w). (Possibly these are global to all threads in a warp?) Add a new register class to handle this. Signed-off-by: Rob Clark <[email protected]>
* freedreno: extract helper for stage->sb for a4xx+Rob Clark2017-04-175-28/+29
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/{a4xx,a5xx}: switch to CP_LOAD_STATE4Rob Clark2017-04-175-127/+124
| | | | | | | The layout of CP_LOAD_STATE packet is slightly different on a4xx+. Switch to the a4xx+ specific CP_LOAD_STATE4 to get the correct encoding. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-04-178-213/+794
| | | | Signed-off-by: Rob Clark <[email protected]>
* gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORTNicolai Hähnle2017-04-141-0/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* freedreno: enable draw/batch reordering by defaultRob Clark2017-04-142-3/+3
| | | | | | | | Probably should have flipped the switch a long time ago, since it doesn't seem to cause any problems and is a nice perf boost in a number of cases. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: small re-orderRob Clark2017-04-141-24/+23
| | | | | | | Small re-order of switch statement to handled op-code categories in order. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move 'keeps' to block levelRob Clark2017-04-145-20/+22
| | | | | | | For things like SSBOs and atomics we'll want to track this at a block level. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: convert dynamic arrays to rallocRob Clark2017-04-143-14/+8
| | | | | | | Want to move one of these under ir3_block, so that gives a reason to migrate the remaining malloc/realloc to ralloc. Signed-off-by: Rob Clark <[email protected]>
* gallium: add PIPE_CAP_TGSI_BALLOTNicolai Hähnle2017-04-051-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: add sparse buffer interface and capabilityNicolai Hähnle2017-04-051-0/+1
| | | | | | | v2: - explain the resource_commit interface in more detail Reviewed-by: Marek Olšák <[email protected]>
* gallium: Add a cap to check if the driver supports fill_rectangleLyude2017-03-311-0/+1
| | | | | | | | Changes since v1: - Add pipe caps for etnaviv, freedreno, swr and virgl Signed-off-by: Lyude <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: remove support for predicates from TGSI (v2)Marek Olšák2017-04-011-2/+0
| | | | | | | | | | | Neved used. v2: gallivm: rename "pred" -> "exec_mask" etnaviv: remove the cap gallium: fix tgsi_instruction::Padding Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add PIPE_CAP_TGSI CLOCKNicolai Hähnle2017-03-311-0/+1
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno: free compiler when screen is destroyedRob Clark2017-03-243-6/+2
| | | | | | | | | | | | Drop ir3_compiler_destroy(), since it is only ralloc_free() and we shouldn't really have an ir3 dependency in core. If some future hw has a new compiler, as long as all it's resources are ralloc()d then things will all just work. (In practice, I suppose you never really see this leak, but removing it at least cleans up some noise in valgrind.) Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix memory leakRob Clark2017-03-241-0/+2
| | | | | | | | | | | | | Otherwise blitter would still hold a ref to, for example, sampler- views. To reproduce: glmark2 -b desktop:duration=2 --run-forever Fixes: a8e6734 ("freedreno: support for using generic clear path") Cc: "13.0 17.0" <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* gallium: add PIPE_CAP_TGSI_TEX_TXF_LZMarek Olšák2017-03-151-0/+1
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* nir: Rework conversion opcodesJason Ekstrand2017-03-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The NIR story on conversion opcodes is a mess. We've had way too many of them, naming is inconsistent, and which ones have explicit sizes was sort-of random. This commit re-organizes things and makes them all consistent: - All non-bool conversion opcodes now have the explicit size in the destination and are named <src_type>2<dst_type><size>. - Integer <-> integer conversion opcodes now only come in i2i and u2u forms (i2u and u2i have been removed) since the only difference between the different integer conversions is whether or not they sign-extend when up-converting. - Boolean conversion opcodes all have the explicit size on the bool and are named <src_type>2<dst_type>. Making things consistent also allows nir_type_conversion_op to be moved to nir_opcodes.c and auto-generated using mako. This will make adding int8, int16, and float16 versions much easier when the time comes. Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: fragz cannot be half precisionRob Clark2017-03-131-0/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: optimize less in glslRob Clark2017-03-131-1/+1
| | | | | | | | | | | | | | | | | | | Rely on nir for optimization, to reduce compile times. Very minimal impact on shader-db: total instructions in shared programs: 104170 -> 104199 (0.03%) total dwords in shared programs: 209664 -> 209728 (0.03%) total full registers used in shared programs: 7156 -> 7161 (0.07%) total half registers used in shader programs: 109 -> 109 (0.00%) total const registers used in shared programs: 24222 -> 24224 (0.01%) half full const instr dwords helped 12 107 103 112 98 hurt 11 104 105 115 102 But shader db runtime dropped from ~29.3s user to ~20.4s user. Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove shebang from ir3_nir_trig.pyEmil Velikov2017-03-101-1/+0
| | | | | | | Analogous to earlier commit(s). Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* freedreno: remove execute bit from ir3_nir_trig.pyEmil Velikov2017-03-101-0/+0
| | | | | | | | The file is meant to be called with $(PYTHON2) and not executed directly. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* gallium: s/uint/enum pipe_render_cond_flag/ for set_render_condition()Brian Paul2017-03-081-1/+1
| | | | Reviewed-by: Edward O'Callaghan <[email protected]>
* gallium: s/uint/enum pipe_shader_type/ for set_constant_buffer()Brian Paul2017-03-081-1/+2
| | | | Reviewed-by: Edward O'Callaghan <[email protected]>
* freedreno: s/unsigned/enum pipe_shader_type/Brian Paul2017-03-081-1/+1
| | | | Reviewed-by: Edward O'Callaghan <[email protected]>
* gallium: s/unsigned/enum pipe_shader_type/ for pipe_screen::get_shader_param()Brian Paul2017-03-081-1/+2
| | | | Reviewed-by: Edward O'Callaghan <[email protected]>
* gallium/util: replace pipe_mutex_unlock() with mtx_unlock()Timothy Arceri2017-03-075-15/+15
| | | | | | | | | | pipe_mutex_unlock() was made unnecessary with fd33a6bcd7f12. Replaced using: find ./src -type f -exec sed -i -- \ 's:pipe_mutex_unlock(\([^)]*\)):mtx_unlock(\&\1):g' {} \; Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: replace pipe_mutex_lock() with mtx_lock()Timothy Arceri2017-03-075-15/+15
| | | | | | | | | | replace pipe_mutex_lock() was made unnecessary with fd33a6bcd7f12. Replaced using: find ./src -type f -exec sed -i -- \ 's:pipe_mutex_lock(\([^)]*\)):mtx_lock(\&\1):g' {} \; Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: replace pipe_mutex_destroy() with mtx_destroy()Timothy Arceri2017-03-071-1/+1
| | | | | | | | | | pipe_mutex_destroy() was made unnecessary with fd33a6bcd7f12. Replace was done with: find ./src -type f -exec sed -i -- \ 's:pipe_mutex_destroy(\([^)]*\)):mtx_destroy(\&\1):g' {} \; Reviewed-by: Marek Olšák <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 07:34:46 +0000