summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/freedreno
Commit message (Collapse)AuthorAgeFilesLines
* freedreno: add missing PIPE_CAP_RESOURCE_FROM_USER_MEMORY to switchIlia Mirkin2015-02-191-0/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add ARB_instanced_arrays supportIlia Mirkin2015-02-192-2/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add support for vertexid and instanceid sysvalsIlia Mirkin2015-02-194-16/+119
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: pass number of instances to drawIlia Mirkin2015-02-198-18/+22
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add ETC2 decoding supportIlia Mirkin2015-02-192-4/+17
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add hardware ETC1 supportIlia Mirkin2015-02-182-0/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: Add MULTISAMPLE_Z_RESOLVE capAxel Davy2015-02-061-0/+1
| | | | | | | | | | | | | | | | Resolving a multisampled depth texture into a single sampled texture is supported on >= SM4.1 hw. It is possible some previous hw support it. The ability was tested on radeonsi and nvc0. Apparently is is also supported for radeon >= r700. This patch adds the MULTISAMPLE_Z_RESOLVE cap and add it to the drivers. It is advertised for drivers for which it is sure the ability is supported. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Axel Davy <[email protected]>
* gallium: add a cap to determine whether the driver supports offset_clampIlia Mirkin2015-02-021-0/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* dir-locals.el: Don't set variables for non-programming modesNeil Roberts2015-02-021-1/+1
| | | | | | | | | | | | | | This limits the style changes to modes inherited from prog-mode. The main reason to do this is to avoid setting fill-column for people using Emacs to edit commit messages because 78 characters is too many to make it wrap properly in git log. Note that makefile-mode also inherits from prog-mode so the fill column should continue to apply there. v2: Apply to all the .dir-locals.el files, not just the one in the root directory. Acked-by: Michel Dänzer <[email protected]>
* freedreno/a4xx: sysmem bypassRob Clark2015-01-201-3/+58
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-01-205-23/+36
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle "holes" in inputsRob Clark2015-01-131-1/+31
| | | | | | | | | | | | If, for example, only the x/y/w components of in.xyzw are actually used, we still need to have a group of four registers and assign all four components. The hardware can't write in.xy and in.w to discontiguous registers. To handle this, pad with a dummy NOP instruction, to keep the neighbor chain contiguous. This fixes a problem noticed with firefox OMTC. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix pos_regid > max_regRob Clark2015-01-074-41/+121
| | | | | | | | | | | | | | We can't (or don't know how to) turn this off. But it can end up being stored to a higher reg # than what the shader uses, leading to corruption. Also we currently aren't clever enough to turn off frag_coord/frag_face if the input is dead-code, so just fixup max_reg/max_half_reg. Re-org this a bit so both vp and fp reg footprint fixup are called by a common fxn used also by ir3_cmdline. Also add a few more output lines for ir3_cmdline to make it easier to see what is going on. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: start on indirect gpr readsRob Clark2015-01-073-8/+146
| | | | | | | | | | | | | | Handle TEMP[ADDR[]] src registers by generating a fanin to group array elements, similarly to how texture fetch instructions work. NOTE: For all the scalar instructions generated for a single tgsi vector operation which uses an array src (or possibly even uses the same array as multiple srcs), re-use the same fanin node. Since a vector operation operates on all components at the same time, it should never see more than one version of the same array. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: make reg array dynamicRob Clark2015-01-074-13/+50
| | | | | | | | | To use fanin's to group registers in an array, we can potentially have a much larger array of registers. Rather than continuing to bump up the array size, just make it dynamically allocated when the instruction is created. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: simplify RARob Clark2015-01-078-777/+622
| | | | | | | | | | | | | | | | | | | | | | Group inputs/outputs, in addition to fanin/fanout, as they must also exist in sequential scalar registers. This lets us simplify RA by working in terms of neighbor groups. NOTE: has the slight problem that it can't optimize out mov's for things like: MOV OUT[n], IN[m] To avoid this, instead of trying to figure out what mov's we can eliminate, we first remove all mov's prior to grouping, and then re-insert mov's as needed while grouping inputs/outputs/fanins. Eventually we'd prefer the frontend to not insert extra mov's in the first place (so we don't have to bother removing them). This is the plan for an eventual NIR based frontend, so separate out the instr grouping (which will still be needed for NIR frontend) from the mov elimination (which won't). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: regmask support for relative addrRob Clark2015-01-072-17/+51
| | | | | | | | For temp arrays, a 32bit mask won't be sufficient.. but otoh we don't need to support an arbitrary mask. So for this case use a simple size field rather than a bitmask. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split up ssa_srcRob Clark2015-01-071-23/+34
| | | | | | | Slight bit of refactoring that will be needed for indirect gpr addressing (TEMP[ADDR[]]). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop instr_clone() stuffRob Clark2015-01-072-49/+17
| | | | | | | Unnecessary and overly complicated. And gets in the way for temp arrays (TEMP[ADDR[]]). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: runtime enable RA debug for DEBUG buildsRob Clark2015-01-071-1/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle relative addr in ir3_dumpRob Clark2015-01-071-1/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: legalize vs unused sam dst componentsRob Clark2015-01-072-2/+9
| | | | | | | | We probably could be more clever elsewhere and mask out components that are not used. But either way, legalize should realize that there is also a write-after-write hazard with texture sample instructions. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: hack for old compilerRob Clark2015-01-071-0/+23
| | | | | | | Old compiler doesn't have ir3_block's.. so we need a special path. This hack can be dropped when ir3_compiler_old is retired. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out legalize passRob Clark2014-12-235-154/+214
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: ra debugRob Clark2014-12-233-17/+61
| | | | | | Some compile time RA debug Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: blend-colorRob Clark2014-12-201-0/+13
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: alpha-testRob Clark2014-12-201-0/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-12-206-61/+151
|
* freedreno/ir3: trans_kill cleanupRob Clark2014-12-201-12/+7
| | | | | | | trans_kill() only handles the single opcode. Drop the remnant of a time when both KILL and KILL_IF were handled by the same fxn. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: hack for standalone compilerRob Clark2014-12-201-1/+5
| | | | | | | | | Standalone compiler doesn't have screen or context. We need to come up with a better way to control the target arch (ie. something that we can control from cmdline w/ standalone compiler) but for now this hack keeps it from segfault'ing. Signed-off-by: Rob Clark <[email protected]>
* gallium: add TGSI_SEMANTIC_VERTEXID_NOBASE and TGSI_SEMANTIC_BASEVERTEXRoland Scheidegger2014-12-161-0/+1
| | | | | | | | | | | | | | | | | | | Plus a new PIPE_CAP_VERTEXID_NOBASE query. The idea is that drivers not supporting vertex ids with base vertex offset applied (so, only support d3d10-style vertex ids) will get such a d3d10-style vertex id instead - with the caveat they'll also need to handle the basevertex system value too (this follows what core mesa already does). Additionally, this is also useful for other state trackers (for instance llvmpipe / draw right now implement the d3d10 behavior on purpose, but with different semantics it can just do both). Doesn't do anything yet. And fix up the docs wrt similar values. v2: incorporate feedback from Brian and others, better names, better docs. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a4xx: mipmapsRob Clark2014-12-134-24/+80
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-12-135-12/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add is_a3xx()/is_a4xx() helpersRob Clark2014-12-133-7/+27
| | | | | | | | A bunch of open-coded 'gpu_id > 300's seems like it will eventually cause problems with future generations. There were already a few minor problems with caps for features that still need additional work on a4xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: helper to calc layer/level offsetRob Clark2014-12-135-21/+31
| | | | | | | Rather than duplicating this everywhere. Especially as on a4xx the layout of layers and levels differs based on texture type. Signed-off-by: Rob Clark <[email protected]>
* gallium: Remove Android files from distribution.Matt Turner2014-12-121-2/+0
| | | | Android builds Mesa from git, so there don't need to be in the tarball.
* freedreno/a4xx: frag-coord / face fixesRob Clark2014-12-091-6/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fix rendering to layer != 0Rob Clark2014-12-091-1/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: temp hack for FLAT varyingsRob Clark2014-12-091-0/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: lower TXP as neededRob Clark2014-12-093-3/+19
| | | | | | On a3xx, lower TXP for 3D textures, on a4xx lower all TXP. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: XA gpu hang at startupRob Clark2014-12-092-1/+9
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: texture fixesRob Clark2014-12-096-7/+54
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: cleanup slice alignment/setupRob Clark2014-12-091-36/+14
| | | | | | | | Collapse things back into a setup_slices() which takes the desired alignment as a param. This gets things ready for a4xx which has some slightly different requirements. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-12-096-18/+65
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: silence warning about missing DEPTH32XIlia Mirkin2014-12-061-1/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle index_bias (i.e. base_vertex)Ilia Mirkin2014-12-061-3/+13
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: add bgr565 texturing and renderingIlia Mirkin2014-12-061-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: add support for SRGB render targetsIlia Mirkin2014-12-062-9/+12
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: output RGBA16_FLOAT from fs for certain outputsIlia Mirkin2014-12-063-1/+17
| | | | | | | Fixes R11G11B10F rendering, and is required for SRGB format support. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: re-enable rgb10_a2 render targetsIlia Mirkin2014-12-061-1/+3
| | | | | | | | There were previously regressions regarding border colors, which the updated swizzle logic resolves. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 11:51:43 +0000