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* freedreno: track staging and shadow perf ctrs for the HUDRob Clark2017-12-175-0/+16
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: staging upload transfersRob Clark2017-12-173-43/+135
| | | | | | | | | | In the busy && !needs_flush case, we can support a DISCARD_RANGE upload using a staging buffer. This is a bit different from the case of mid- batch uploads which require us to shadow the whole resource (because later draws in an earlier tile happen before earlier draws in a later tile). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-12-177-63/+334
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: use u_transfer_helperRob Clark2017-12-152-229/+44
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: hide ARB_base_instanceRob Clark2017-12-051-1/+8
| | | | | | Grrr.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle input/output componentRob Clark2017-12-051-4/+6
| | | | | | | | | | | | | | | | | After the mesa/st nir linking support, we start to see inputs/outputs like: decl_var shader_out INTERP_MODE_NONE float packed:uv (VARYING_SLOT_VAR9.x, 1, 0) decl_var shader_out INTERP_MODE_NONE float packed:uv@0 (VARYING_SLOT_VAR9.y, 1, 0) (ie. were location_frac != .x) Unfortunately I overlooked the addition of the component parameter to load_input/store_output, so when we started encountering inputs/outputs with component other than .x, we'd end up loading/storing the wrong input/output. Signed-off-by: Rob Clark <[email protected]>
* gallium/u_upload_mgr: allow drivers to specify pipe_resource::flagsMarek Olšák2017-12-053-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: define driver dependenciesDylan Baker2017-12-041-0/+5
| | | | | | | | | | | | This allow us to encapsulate the compiler and linkage requirements of each driver in a reusable way. The result will be that each target that needs a specific driver can simply add `driver_<name>` to its dependencies line and the necessary libraries and compiler args will be added. This will allow for a lot of code de-duplication between gallium targets. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* freedreno: mark stencil buffer valid too in case of z32x24s8Rob Clark2017-12-042-2/+4
| | | | | | | | | | | | The separate stencil buffer was not also getting marked as valid if written by a draw/clear, resulting in gmem2mem getting skipped. Move this into fd_batch_resource_used() which also handles the separate stencil case. Also fix restore_buffers typo. Fixes: 4ab6ab80365 freedreno: avoid mem2gmem for invalidated buffers Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove use of u_transferRob Clark2017-12-0411-41/+30
| | | | | | | Freedreno doesn't treat buffers and images differently, so it's use was kind of pointless. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add -Wno-packed-bitfield-compat for meson buildEric Engestrom2017-12-041-2/+12
| | | | | | | | | | | Otherwise huge amount of spam from instr-a2xx.h.. gcc has no way to know that freedreno was never built with such an old gcc version to care about the bugs in old gcc ;-) Reported-by: Rob Clark <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> [added commit message] Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: relax barriersRob Clark2017-12-031-2/+2
| | | | | | Instructions with no barrier_class can move wrt. an EVERYTHING barrier. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: all mem instructions have WAR hazzardRob Clark2017-12-031-1/+1
| | | | | | | | It isn't just load instructions that have write-after-read hazzard. Fixes stk gaussian blur compute shaders. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add debug option to force emulated indirectRob Clark2017-12-033-0/+12
| | | | | | Useful mostly for debugging indirect draw. Signed-off-by: Rob Clark <[email protected]>
* freedreno: also mark draw-indirect buffer as readRob Clark2017-12-031-0/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: small cleanupsRob Clark2017-12-031-17/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: avoid unneccessary batch flushRob Clark2017-12-031-0/+2
| | | | | | | | | In some cases we can end up trying to add a write dependency on ourself, which shouldn't trigger a flush. Avoids an extra couple flushes per from in stk. Signed-off-by: Rob Clark <[email protected]>
* freedreno: avoid mem2gmem for invalidated buffersRob Clark2017-12-033-2/+17
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: deferred flush supportRob Clark2017-12-035-4/+32
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: rework fence trackingRob Clark2017-12-0312-61/+109
| | | | | | | | | ctx->last_fence isn't such a terribly clever idea, if batches can be flushed out of order. Instead, each batch now holds a fence, which is created before the batch is flushed (useful for next patch), that later gets populated after the batch is actually flushed. Signed-off-by: Rob Clark <[email protected]>
* freedreno: proper locking for iterating dependent batchesRob Clark2017-12-032-8/+20
| | | | | | | | | In transfer_map(), when we need to flush batches that read from a resource, we should be holding screen->lock to guard against race conditions. Somehow deferred flush seems to make this existing race more obvious. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: correct max_indicies for indirect drawsRob Clark2017-12-031-1/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* meson: use dep_thread instead of dependency('threads') in freedrenoDylan Baker2017-12-011-1/+1
| | | | | | | | They are the same thing, but this is more consistent with the rest of the project. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* meson: Add lmsensors supportDylan Baker2017-12-011-0/+1
| | | | | | | | v2: - Make -Dlmsensors=false work - Simplify auto and true cases Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* freedreno/a4xx: add ARB_framebuffer_no_attachments supportIlia Mirkin2017-11-252-1/+6
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a4xx: add indirect draw supportIlia Mirkin2017-11-252-0/+33
| | | | | | | | This is a copy of the a5xx logic. Fails a few tests, but basic functionality is there. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: regenerate pm4 header, adjust code for new namesIlia Mirkin2017-11-253-114/+171
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a4xx: add stencil texturing supportIlia Mirkin2017-11-253-12/+35
| | | | | | | Copied from a5xx, should be identical. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/ir3: add a pass to lower tg4 to txl, enable gather on a4xxIlia Mirkin2017-11-257-3/+151
| | | | | | | | | | Unfortunately Adreno A4xx hardware returns incorrect results with the GATHER4 opcodes. As a result, we have to lower to 4 individual texture calls (txl since we have to force lod to 0). We achieve this using offsets, including on cube maps which normally never have offsets. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/ir3: add texture gather supportRob Clark2017-11-182-2/+17
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: stencil texturing supportRob Clark2017-11-173-10/+34
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx/gmem: fix z32/s8 restore/resolveRob Clark2017-11-171-5/+13
| | | | | | | BLIT_ZS mode is used for either combined z24/s8 or z32 in which case BLIT_S mode is used for separate stencil. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx/gmem: move ZS restore tiling hackRob Clark2017-11-171-20/+22
| | | | | | Code motion to simplify next patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-11-176-13/+13
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* freedreno: also mark images used by draw/gridRob Clark2017-11-161-0/+18
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: mark SSBOs written at draw timeRob Clark2017-11-161-1/+1
| | | | | | Comment was right, implementation was wrong ;-) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: ARB_framebuffer_no_attachments supportRob Clark2017-11-163-1/+11
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: small comment fixRob Clark2017-11-141-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: indirect draw supportRob Clark2017-11-142-1/+37
| | | | | | | | | A couple failures in piglit tests w/ TF or gl_VertexID + indirect draws. OTOH all the deqp tests (although they don't test those combinations). I suspect this could be fixed by a firmware update, but I don't think there is much we can do in mesa for that. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: split out helper for pipeline stallsRob Clark2017-11-142-6/+13
| | | | | | We need a similar thing for indirect draws. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-11-146-16/+135
| | | | Signed-off-by: Rob Clark <[email protected]>
* meson: don't use build_by_default for specific gallium driversDylan Baker2017-11-131-1/+0
| | | | | | | | | | | | | | | | | | | Using build_by_default : false is convenient for dependencies that can be pulled in by various diverse components of the build system, the gallium hardware/software drivers and state trackers do not fit that description. Instead, these should be guarded using the variable that tracks whether that driver should be enabled. This leaves a few helper libraries: trace, rbug, etc, and the generic winsys bits as `build_by_default : false` because there are a large number of gallium components that pull them in. v2: - remove build_by_default from winsys convenience libs as well. v3: - Always put drivers before winsys for consistency Signed-off-by: Dylan Baker <[email protected]> Tested-by: Lionel Landwerlin <[email protected]> (v1) Reviewed-by: Eric Anholt <[email protected]>
* freedreno/a5xx: fix SSBO emit for non-zero offsetRob Clark2017-11-121-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: remove obsolete commentRob Clark2017-11-121-4/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't create split/fo if only writing .xRob Clark2017-11-121-0/+6
| | | | | | | In case an instruction only writes one register, and it is .x, we can skip the extra level of fanout indirection. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: indirect gridsRob Clark2017-11-123-20/+86
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: add global size compute capRob Clark2017-11-121-0/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: turn on std430 packingRob Clark2017-11-121-1/+6
| | | | | | Seems to fix dEQP compute related tests.. and matches what i965 does, so perhaps there is some assumption that std430 packing is on by default somewhere in NIR?
* freedreno/a5xx: image supportRob Clark2017-11-128-31/+306
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* freedreno/ir3: moar better schedulerRob Clark2017-11-125-58/+227
| | | | | | | | | | | | | | | | | | Add a new pass that inserts additional dependencies, rather than simply relying on SSA srcs added in the nir->ir3 frontend. This makes it easier to deal with barriers, but the additional false deps also lets us deal properly with ensuring a write depends on all previous reads. Since conversion to barrier instructions is lossy (ie. just knowing the instruction doesn't tell us enough about what other instructions the barrier applies to), use barrier_class/barrier_conflict fields in the ir3_instruction to retain this information. This could probably be relaxed somewhat by considering *which* array/ buffer/image variable is being referenced. Ie. a write to buffer A can overtake a read from buffer B, if B is not coherent. (right?) Signed-off-by: Rob Clark <[email protected]>
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