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* android: use LOCAL_SHARED_LIBRARIES over TARGET_OUT_HEADERSEmil Velikov2015-04-221-3/+2
| | | | | | | | | | ... to manage the LIBDRM*_CFLAGS. The former is the recommended approach by the Android build system developers while the latter has been depreciated for quite some time. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 86919352e3da1c80409fdcb67c36f29a9687b7a9)
* freedreno/a3xx: point size should not be divided by 2Ilia Mirkin2015-04-082-5/+5
| | | | | | | | | | | | The division is probably a holdover from the days when the fixed point inline functions generated by headergen were broken. Also reduce the maximum point size to 4092 (vs 4096), which is what the blob does. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> (cherry picked from commit 7fc5da8b9392042b5f8a989d2afa49ea1944f9a9)
* freedreno/a3xx: fix 3d texture layoutIlia Mirkin2015-04-082-7/+16
| | | | | | | | | | | | | | The SZ2 field contains the layer size of a lower miplevel. It only contains 4 bits, which limits the maximum layer size it can describe. In situations where the next miplevel would be too big, the hardware appears to keep minifying the size until it hits one of that size. Unfortunately the hardware's ideas about sizes can differ from freedreno's which can still lead to issues. Minimize those by stopping to minify as soon as possible. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.5" <[email protected]> (cherry picked from commit 738c8319ac85b175994b35d1fdc4860e18184b93)
* freedreno: update generated headersRob Clark2015-03-255-6/+6
| | | | | | | | Fix a3xx texture layer-size. Signed-off-by: Rob Clark <[email protected]> Cc: "10.4 10.5" <[email protected]> (cherry picked from commit e92bc6b38e90339a394e95a562bcce35c3ee9696)
* freedreno: fix slice pitch calculationsIlia Mirkin2015-03-251-1/+1
| | | | | | | | | | | | | | For example if width were 65, the first slice would get 96 while the second would get 32. However the hardware appears to expect the second pitch to be 64, based on halving the 96 (and aligning up to 32). This fixes texelFetch piglit tests on a3xx below a certain size. Going higher they break again, but most likely due to unrelated reasons. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.5" <[email protected]> Reviewed-by: Rob Clark <[email protected]> (cherry picked from commit 620e29b74821fd75b24495ab2bfddea53fc75350)
* freedreno/a3xx: use the same layer size for all slicesIlia Mirkin2015-03-251-1/+8
| | | | | | | | | | | | | | | | | | | We only program in one layer size per texture, so that means that all levels must share one size. This makes the piglit test bin/texelFetch fs sampler2DArray have the same breakage as its non-array version instead of being completely off, and makes bin/ext_texture_array-gen-mipmap start passing. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.5" <[email protected]> Reviewed-by: Rob Clark <[email protected]> (cherry picked from commit 89b26d5a360ebde11a69f2cdefa66e4d6a2a13fd)
* freedreno/ir3: fix failed assert in groupingRob Clark2015-03-121-27/+44
| | | | | | | | | | | | | | | | | | | | | | Turns out there are scenarios where we need to insert mov's in "front" of an input. Triggered by shaders like: VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL SAMP[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyyy 1: MOV TEMP[0].w, IN[1].wwww 2: TXF TEMP[0], TEMP[0], SAMP[0], 1D_ARRAY 3: MOV OUT[1], TEMP[0] 4: MOV OUT[0], IN[0] 5: END Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit 27648efa2070e8db111908314d8b924d3717dbb0)
* freedreno/ir3: handle flat bypass for a4xxRob Clark2015-03-128-5/+99
| | | | | | | | | | | | We may not need this for later a4xx patchlevels, but we do at least need this for patchlevel 0. Bypass bary.f for fetching varyings when flat shading is needed (rather than configure via cmdstream). This requires a special dummy bary.f w/ (ei) flag to signal to scheduler when all varyings are consumed. And requires shader variants based on rasterizer flatshade state to handle TGSI_INTERPOLATE_COLOR. Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit e9f2abe349886ae5423c7c31d201e7d587a3695a)
* freedreno/ir3: add support for memory (cat6) instructionsRob Clark2015-03-123-1/+8
| | | | | | | | Scheduled basically the same as texture (cat5) instructions, using (sy) flag for synchronization. Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit 9d732d3125e1b39788a642a5723aeb54cb1983f3)
* freedreno/ir3: fix up cat6 instruction encodingsRob Clark2015-03-123-139/+121
| | | | | | | | I think there is at least one more sub-encoding, but these two should be enough to cover the common load/store instructions. Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit 20b50a071271e2caf8a4c3d4fd72f877af8a18d9)
* freedreno/a4xx: aniso filteringRob Clark2015-03-121-4/+6
| | | | | Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit dd70e786747f7e4800f4bba245373c5ffa3baeee)
* freedreno: update generated headersRob Clark2015-03-125-5/+20
| | | | | Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit c70097ae8655d84a900cb27d165ca59d66411e29)
* freedreno/a4xx: set PC_PRIM_VTX_CNTL.VAROUT properlyRob Clark2015-03-121-1/+6
| | | | | | | | Fixes xonotic, some webgl stuff, and really pretty much anything with more than 4 varyings. Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit 51e335742e55d6725fd5c4558158769a32f70f22)
* freedreno: update generated headersRob Clark2015-03-127-16/+45
| | | | | | | | Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit fb1301e40abbac1de973563cacd2c7f31aa6bb4f) Conflicts: src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
* freedreno/a4xx: bit of cleanupRob Clark2015-03-124-33/+27
| | | | | Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit bdf023482a6fd07adef090fb66a4aaaac22810fc)
* freedreno/a2xx: fix increment in assertRob Clark2015-03-121-1/+2
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88883 Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit 68552266535747bad1eff34d856c43158398b9bf)
* freedreno/ir3: fix silly typo for binning pass shadersRob Clark2015-03-111-1/+1
| | | | | | | | | | Was resulting in gl_PointSize write being optimized out, causing particle system type shaders to hang if hw binning enabled. Fixes neverball, OGLES2ParticleSystem, etc. Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit 60096ed906e5ebfdce41024c7af69f03b96dbe82)
* freedreno/ir3: get the # of miplevels from getinfoIlia Mirkin2015-03-111-0/+20
| | | | | | | | | | This fixes ARB_texture_query_levels to actually return the desired value. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Cc: "10.4 10.5" <[email protected]> (cherry picked from commit cb3eb43ad690a7355429ba8dcd40120646c55b9c)
* freedreno/ir3: fix array count returned by TXQIlia Mirkin2015-03-111-2/+42
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Cc: "10.4 10.5" <[email protected]> (cherry picked from commit 8ac957a51c67fc095db9539df6482b9533b1d05c)
* freedreno: move fb state copy after checking for size changeIlia Mirkin2015-03-111-2/+2
| | | | | | | | Fixes: 1f3ca56b ("freedreno: use util_copy_framebuffer_state()") Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Cc: "10.4 10.5" <[email protected]> (cherry picked from commit f3dfe6513c26d1ce50b3b0fc830d4d8ff7f6b922)
* gallium: Add MULTISAMPLE_Z_RESOLVE capAxel Davy2015-02-061-0/+1
| | | | | | | | | | | | | | | | Resolving a multisampled depth texture into a single sampled texture is supported on >= SM4.1 hw. It is possible some previous hw support it. The ability was tested on radeonsi and nvc0. Apparently is is also supported for radeon >= r700. This patch adds the MULTISAMPLE_Z_RESOLVE cap and add it to the drivers. It is advertised for drivers for which it is sure the ability is supported. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Axel Davy <[email protected]>
* gallium: add a cap to determine whether the driver supports offset_clampIlia Mirkin2015-02-021-0/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* dir-locals.el: Don't set variables for non-programming modesNeil Roberts2015-02-021-1/+1
| | | | | | | | | | | | | | This limits the style changes to modes inherited from prog-mode. The main reason to do this is to avoid setting fill-column for people using Emacs to edit commit messages because 78 characters is too many to make it wrap properly in git log. Note that makefile-mode also inherits from prog-mode so the fill column should continue to apply there. v2: Apply to all the .dir-locals.el files, not just the one in the root directory. Acked-by: Michel Dänzer <[email protected]>
* freedreno/a4xx: sysmem bypassRob Clark2015-01-201-3/+58
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-01-205-23/+36
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle "holes" in inputsRob Clark2015-01-131-1/+31
| | | | | | | | | | | | If, for example, only the x/y/w components of in.xyzw are actually used, we still need to have a group of four registers and assign all four components. The hardware can't write in.xy and in.w to discontiguous registers. To handle this, pad with a dummy NOP instruction, to keep the neighbor chain contiguous. This fixes a problem noticed with firefox OMTC. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix pos_regid > max_regRob Clark2015-01-074-41/+121
| | | | | | | | | | | | | | We can't (or don't know how to) turn this off. But it can end up being stored to a higher reg # than what the shader uses, leading to corruption. Also we currently aren't clever enough to turn off frag_coord/frag_face if the input is dead-code, so just fixup max_reg/max_half_reg. Re-org this a bit so both vp and fp reg footprint fixup are called by a common fxn used also by ir3_cmdline. Also add a few more output lines for ir3_cmdline to make it easier to see what is going on. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: start on indirect gpr readsRob Clark2015-01-073-8/+146
| | | | | | | | | | | | | | Handle TEMP[ADDR[]] src registers by generating a fanin to group array elements, similarly to how texture fetch instructions work. NOTE: For all the scalar instructions generated for a single tgsi vector operation which uses an array src (or possibly even uses the same array as multiple srcs), re-use the same fanin node. Since a vector operation operates on all components at the same time, it should never see more than one version of the same array. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: make reg array dynamicRob Clark2015-01-074-13/+50
| | | | | | | | | To use fanin's to group registers in an array, we can potentially have a much larger array of registers. Rather than continuing to bump up the array size, just make it dynamically allocated when the instruction is created. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: simplify RARob Clark2015-01-078-777/+622
| | | | | | | | | | | | | | | | | | | | | | Group inputs/outputs, in addition to fanin/fanout, as they must also exist in sequential scalar registers. This lets us simplify RA by working in terms of neighbor groups. NOTE: has the slight problem that it can't optimize out mov's for things like: MOV OUT[n], IN[m] To avoid this, instead of trying to figure out what mov's we can eliminate, we first remove all mov's prior to grouping, and then re-insert mov's as needed while grouping inputs/outputs/fanins. Eventually we'd prefer the frontend to not insert extra mov's in the first place (so we don't have to bother removing them). This is the plan for an eventual NIR based frontend, so separate out the instr grouping (which will still be needed for NIR frontend) from the mov elimination (which won't). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: regmask support for relative addrRob Clark2015-01-072-17/+51
| | | | | | | | For temp arrays, a 32bit mask won't be sufficient.. but otoh we don't need to support an arbitrary mask. So for this case use a simple size field rather than a bitmask. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split up ssa_srcRob Clark2015-01-071-23/+34
| | | | | | | Slight bit of refactoring that will be needed for indirect gpr addressing (TEMP[ADDR[]]). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop instr_clone() stuffRob Clark2015-01-072-49/+17
| | | | | | | Unnecessary and overly complicated. And gets in the way for temp arrays (TEMP[ADDR[]]). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: runtime enable RA debug for DEBUG buildsRob Clark2015-01-071-1/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle relative addr in ir3_dumpRob Clark2015-01-071-1/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: legalize vs unused sam dst componentsRob Clark2015-01-072-2/+9
| | | | | | | | We probably could be more clever elsewhere and mask out components that are not used. But either way, legalize should realize that there is also a write-after-write hazard with texture sample instructions. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: hack for old compilerRob Clark2015-01-071-0/+23
| | | | | | | Old compiler doesn't have ir3_block's.. so we need a special path. This hack can be dropped when ir3_compiler_old is retired. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out legalize passRob Clark2014-12-235-154/+214
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: ra debugRob Clark2014-12-233-17/+61
| | | | | | Some compile time RA debug Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: blend-colorRob Clark2014-12-201-0/+13
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: alpha-testRob Clark2014-12-201-0/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-12-206-61/+151
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* freedreno/ir3: trans_kill cleanupRob Clark2014-12-201-12/+7
| | | | | | | trans_kill() only handles the single opcode. Drop the remnant of a time when both KILL and KILL_IF were handled by the same fxn. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: hack for standalone compilerRob Clark2014-12-201-1/+5
| | | | | | | | | Standalone compiler doesn't have screen or context. We need to come up with a better way to control the target arch (ie. something that we can control from cmdline w/ standalone compiler) but for now this hack keeps it from segfault'ing. Signed-off-by: Rob Clark <[email protected]>
* gallium: add TGSI_SEMANTIC_VERTEXID_NOBASE and TGSI_SEMANTIC_BASEVERTEXRoland Scheidegger2014-12-161-0/+1
| | | | | | | | | | | | | | | | | | | Plus a new PIPE_CAP_VERTEXID_NOBASE query. The idea is that drivers not supporting vertex ids with base vertex offset applied (so, only support d3d10-style vertex ids) will get such a d3d10-style vertex id instead - with the caveat they'll also need to handle the basevertex system value too (this follows what core mesa already does). Additionally, this is also useful for other state trackers (for instance llvmpipe / draw right now implement the d3d10 behavior on purpose, but with different semantics it can just do both). Doesn't do anything yet. And fix up the docs wrt similar values. v2: incorporate feedback from Brian and others, better names, better docs. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a4xx: mipmapsRob Clark2014-12-134-24/+80
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-12-135-12/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add is_a3xx()/is_a4xx() helpersRob Clark2014-12-133-7/+27
| | | | | | | | A bunch of open-coded 'gpu_id > 300's seems like it will eventually cause problems with future generations. There were already a few minor problems with caps for features that still need additional work on a4xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: helper to calc layer/level offsetRob Clark2014-12-135-21/+31
| | | | | | | Rather than duplicating this everywhere. Especially as on a4xx the layout of layers and levels differs based on texture type. Signed-off-by: Rob Clark <[email protected]>
* gallium: Remove Android files from distribution.Matt Turner2014-12-121-2/+0
| | | | Android builds Mesa from git, so there don't need to be in the tarball.
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