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* util/ra: Make allocating conflict lists optionalJason Ekstrand2015-08-181-1/+1
| | | | | | | | | Since i965 is now using make_reg_conflicts_transitive and doesn't need q-value computations, they are disabled on i965. They are enabled everywhere else so that they get the old behavior. This reduces the time spent in eglInitialize() on BDW by around 10-15%. Reviewed-by: Eric Anholt <[email protected]>
* freedreno/a4xx: add cube map array supportIlia Mirkin2015-08-151-0/+11
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: 'keeps' need neighbors found tooRob Clark2015-08-121-0/+5
| | | | | | | | | This shows up with a glamor shader, which does a TXF and uses the result for conditional kill. Before we wouldn't group the fanin (collect) neighbors which need to be allocated adjacently at RA, resulting in badness. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/print: print left/right neighbors tooRob Clark2015-08-121-0/+14
| | | | | | When debugging compiler, this is useful to see. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use nir pass to lower const to scalarRob Clark2015-08-121-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: point-size and spritelist fixesRob Clark2015-08-121-5/+0
| | | | | | | | | a4xx needs similar treatment as 995f55a6 Also fixup a few point-size and vpsrepl issues and drop fix_blit_fp() hack previously needed for mem2gmem. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add transform-feedback supportRob Clark2015-07-273-4/+219
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: track "keeps" in irRob Clark2015-07-274-23/+17
| | | | | | | | | | | | Previously we had a fixed array to track kills, since they don't generate an SSA value, and then cheated by stuffing them in the outputs array before sending things through depth/sched/etc. But store instructions will need similar treatment. So convert this over to a more general array of instructions that must be kept and fix up the places that were previously relying on kills being in the output array. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add support for store instructionsRob Clark2015-07-273-6/+43
| | | | | | | | | | For store instructions, the "dst" register is a read register, not a written register. (Ie. it is the address to store to.) Lets not confuse register allocation, scheduling, etc, with these details. Instead just leave a dummy instr->regs[0], and take "dst" from instr->regs[1] and srcs following. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cleanup driver-param stuffRob Clark2015-07-273-10/+31
| | | | | | | | | Add 'enum ir3_driver_param' to track driver-param slots, and a create_driver_param() helper to avoid having the knowledge about where driver params are placed in const regs spread throughout the code as we add additional driver-params. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx+a4xx: add support for vtxcnt semanticRob Clark2015-07-271-0/+5
| | | | | | This will be used for stream-out (transform-feedback) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add stream-output support to cmdline compilerRob Clark2015-07-271-4/+22
| | | | | | A bit hard-coded configuration at the moment, but sufficient for now. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop unused create_input() argRob Clark2015-07-271-11/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move emit_const to ir3Rob Clark2015-07-272-0/+152
| | | | | | | | | | | | | | | Details of the cmdstream packets are different between a3xx and a4xx, but the logic about the layout of const registers is the same, as that is dictated by the ir3 shader compiler. So rather than duplicating logic that is tightly coupled to ir3 between a3xx and a4xx, move this into ir3 and use per-generation callbacks for to build the cmdstream packets. This should make it easier to pass additional const regs (such as for transform feedback). And it also keeps the layout internal to ir3 in case we want to make the layout more dynamic some day. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: bit of shader API refactoringRob Clark2015-07-275-20/+23
| | | | | | | | | | | | Since for transform-feedback, we'll need more than just the TGSI tokens from the state object, just pass the entire state object to ir3_shader_create(). This also cleans things up a bit for some day in the future when we could take shader either as TGSI or directly NIR (for ex, glsl2nir or spirv2nir paths). In the same spirit, drop extra args from ir3_compile_shader_nir() (since it can anyways get what it needs from the ir3_shader_variant). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: updated cat6 encodingRob Clark2015-07-275-113/+230
| | | | | | | Sync updated cat6 encoding from freedreno.git, needed to properly encode store instructions. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: fixup new instr's blockRob Clark2015-07-101-0/+4
| | | | | | | | | | | | If we split addr/pred, the original instruction could have originated from a different block. If we don't fixup the block ptr we hit asserts later (in debug builds). NOTE: perhaps we don't want to try to preserve addr/pred reg's across block boundaries.. this at least needs some thought in case addr/pred writes end up inside a conditional block.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/ra: fix failed assert for a0/p0Rob Clark2015-07-101-0/+5
| | | | | | | | The address and predicate register are special, they don't get assigned in RA. So do a better job of ignoring them rather than hitting later asserts. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: shader-db tracesRob Clark2015-07-105-8/+65
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't be confused by eliminated indirectsRob Clark2015-07-032-0/+14
| | | | | | | | If an instruction using address register value gets eliminated, we need to remove it from the indirects list, otherwise it causes mayhem in sched for scheduling address register usage. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: sched fixes for addr register usageRob Clark2015-07-031-12/+65
| | | | | | | | | | | | | | | | A handful of fixes and cleanups: 1) If we split addr/pred, we need the newly created instruction to end up in the unscheduled_list 2) Avoid scheduling a write to the address register if there is no instruction using the address register that is otherwise ready to schedule. Note that I currently don't bother with the same logic for predicate register, since the only instructions using predicate (br/kill) don't take any other src registers, so this situation should not arise. 3) few other cosmetic cleanups Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix indirects trackingRob Clark2015-07-035-10/+23
| | | | | | | | | | cp would update instr->address but not update the indirects array resulting in sched getting confused when it had to 'spill' the address register. Add an ir3_instr_set_address() helper to set instr->address and also update ir->indirects, and update all places that were writing instr->address to use helper instead. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: mark location specially in nir for color0-writes-allIlia Mirkin2015-07-031-0/+4
| | | | | | | | | | We need to distinguish a shader that has separate writes to each MRT from one which is supposed to write the data from MRT 0 to all the MRTs. In TGSI this is done with a property. NIR doesn't have that, so encode it as a funny location and decode on the other end. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: cache defining instructionRob Clark2015-06-303-69/+91
| | | | | | | | | It is silly to traverse back to find first instruction that writes part of a larger "virtual" register many times per instruction (plus per use as a src to later instructions). Cache this information so we only figure it out once. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix RA issue with faninRob Clark2015-06-301-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | The fanin source could be grouped, for example with shaders like: VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyyy 1: MOV TEMP[0].w, IN[1].wwww 2: TXF TEMP[0], TEMP[0], SAMP[0], 2D 3: MOV OUT[1], TEMP[0] 4: MOV OUT[0], IN[0] 5: END The second arg to the isaml is IN[1].w, so we need to look at the fanin source to get the correct offset. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add ir3_shader_disasm()Rob Clark2015-06-303-120/+124
| | | | | | | | | Split out most of dump_info() from ir3_cmdline compiler into a function that can be used both by cmdline compiler and also for the disasm debug option. This way, for FD_MESA_DEBUG=disasm we also get to see intput/ output registers, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix crash in fail pathRob Clark2015-06-301-3/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix crash in RARob Clark2015-06-301-2/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fixes for indirect writesRob Clark2015-06-303-4/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix constlen in case of load_uniform_indirectRob Clark2015-06-301-0/+5
| | | | | | | | We can't rely on what we get from the assembler if we have indirect addressing of constant file, since the assembler doesn't know the array index. This got lost in the transition to NIR. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: pass sz to split_dest()Rob Clark2015-06-212-5/+7
| | | | | | | | | | | | | | | | | | | | For query_levels, we generate a getinfo with writemask of (z), which RA will consider as size==3. But we were still generating four fanouts. Which meant that RA would see it as two different register classes, depending on the path to definer. Ie. on the getinfo instruction itself it would see size==3, but when chasing back through the fanouts it would see size==4. Easiest way to solve that is to just generate the chain of neighboring fanouts to have the correct size in the first place. Note: we may eventually want split_dest() to take start/end or wrmask instead, since really we only need size==1. But RA is not clever enough for that, query_levels is not that common, and the other two registers that get allocated are never used so those register slots can be immediately re-used. So bunch of work for probably no real gain. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: add more opcodesRob Clark2015-06-211-1/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: only unminify txf coords on a3xxRob Clark2015-06-211-1/+9
| | | | | | Seems like a4xx gets this right. Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove int sampler shader variantsRob Clark2015-06-212-17/+0
| | | | | | | | We get this information from NIR (which gets it from sview decl in tgsi when translating from tgsi), so no need to maintain shader variants for this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: block reshuffling and loops!Rob Clark2015-06-2110-126/+1025
| | | | | | | | | | | | | | | | This shuffles things around to allow the shader to have multiple basic blocks. We drop the entire CFG structure from nir and just preserve the blocks. At scheduling we know whether to schedule conditional branches or unconditional jumps at the end of the block based on the # of block successors. (Dropping jumps to the following instruction, etc.) One slight complication is that variables (load_var/store_var, ie. arrays) are not in SSA form, so we have to figure out where to put the phi's ourself. For this, we use the predecessor set information from nir_block. (We could perhaps use NIR's dominance frontier information to help with this?) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: a4xx encodes larger immed offsetRob Clark2015-06-214-7/+21
| | | | | | | Without this, negative branch/jump offsets look like very large positive offsets. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: simplify find_neighbors stop conditionRob Clark2015-06-211-17/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move inputs/outputs to shaderRob Clark2015-06-2111-174/+158
| | | | | | | | | These belong in the shader, rather than the block. Mostly a lot of churn and nothing too interesting. But splitting this out from the rest of ir3_block reshuffling to cut down the noise in the later patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/ra: use register_allocateRob Clark2015-06-216-481/+590
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: introduce ir3_compiler objectRob Clark2015-06-218-28/+78
| | | | | | | | Right now, just provides a cleaner way to get at the gpu-id, given the separation between compiler and context. But we will need this also to hold the reg-set for new register allocation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: dump nocp optionRob Clark2015-06-211-6/+0
| | | | | | No longer used, or even possible, with NIR frontend. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: silence warningsRob Clark2015-06-211-1/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove tgsi f/eRob Clark2015-06-219-3953/+25
| | | | | | Also remove ir3_flatten which was only used by tgsi f/e. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: convert to priority queueRob Clark2015-06-214-229/+242
| | | | | | | | Use a more standard priority-queue based scheduling algo. It is simpler and will make things easier once we have multiple basic blocks and flow control. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use standard list implementationRob Clark2015-06-218-209/+161
| | | | | | | | | | Use standard list_head double-linked list and related iterators, helpers, etc, rather than weird combo of instruction array and next pointers depending on stage. Now block has an instrs_list. In certain stages where we want to remove and re-add to the blocks list we just use list_replace() to copy the list to a new list_head. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop dot graph dumpingRob Clark2015-06-217-522/+227
| | | | | | | | At least for now.. right now the instruction and instruction list printing should suffice, and the re-working of ir3_block would require a lot of changes in that code. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: more builder helpersRob Clark2015-06-214-21/+16
| | | | | | | | Use ir3_MOV() builder in a couple of spots, rather than open-coding the instruction construction. Also add ir3_NOP() builder and use that instead of open coding. Signed-off-by: Rob Clark <[email protected]>
* mesa; add a dummy _mesa_error_no_memory() symbol to libglsl_utilEmil Velikov2015-06-121-8/+0
| | | | | | | | | | | | Rather than forcing everyone to provide their own definition of the symbol provide a common (dummy) one. This helps us resolve the build of the standalone pipe-drivers (amongst others), which are missing the symbol. Cc: Rob Clark <[email protected]> Cc: "10.6" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* freedreno/ir3: fix immediate usage in tgsi tex feIlia Mirkin2015-05-201-5/+9
| | | | | | | | get_immediate will return a const reference, the requested immediate isn't necessarily in the x slot. Make sure to use the swizzle. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nir: Get rid of the array elements parameter on load/store intrinsicsJason Ekstrand2015-05-201-5/+0
| | | | | | | | | | | | | Previously, we used intrinsic->const_index[1] to represent "the number of array elements to load" for load/store intrinsics. However, this set to 1 by every pass that ever creates a load/store intrinsic. Also, while it might make some sense for registers, it makes no sense whatsoever in SSA. On top of that, the i965 backend was the only backend to ever support it; freedreno and vc4 just assert that it's always 1. Let's just delete it. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Rob Clark <[email protected]>
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