summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/freedreno/ir3/ir3.h
Commit message (Collapse)AuthorAgeFilesLines
* freedreno/ir3: track "keeps" in irRob Clark2015-07-271-0/+6
| | | | | | | | | | | | Previously we had a fixed array to track kills, since they don't generate an SSA value, and then cheated by stuffing them in the outputs array before sending things through depth/sched/etc. But store instructions will need similar treatment. So convert this over to a more general array of instructions that must be kept and fix up the places that were previously relying on kills being in the output array. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add support for store instructionsRob Clark2015-07-271-0/+21
| | | | | | | | | | For store instructions, the "dst" register is a read register, not a written register. (Ie. it is the address to store to.) Lets not confuse register allocation, scheduling, etc, with these details. Instead just leave a dummy instr->regs[0], and take "dst" from instr->regs[1] and srcs following. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: updated cat6 encodingRob Clark2015-07-271-1/+3
| | | | | | | Sync updated cat6 encoding from freedreno.git, needed to properly encode store instructions. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix indirects trackingRob Clark2015-07-031-0/+5
| | | | | | | | | | cp would update instr->address but not update the indirects array resulting in sched getting confused when it had to 'spill' the address register. Add an ir3_instr_set_address() helper to set instr->address and also update ir->indirects, and update all places that were writing instr->address to use helper instead. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cache defining instructionRob Clark2015-06-301-1/+1
| | | | | | | | | It is silly to traverse back to find first instruction that writes part of a larger "virtual" register many times per instruction (plus per use as a src to later instructions). Cache this information so we only figure it out once. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: block reshuffling and loops!Rob Clark2015-06-211-24/+68
| | | | | | | | | | | | | | | | This shuffles things around to allow the shader to have multiple basic blocks. We drop the entire CFG structure from nir and just preserve the blocks. At scheduling we know whether to schedule conditional branches or unconditional jumps at the end of the block based on the # of block successors. (Dropping jumps to the following instruction, etc.) One slight complication is that variables (load_var/store_var, ie. arrays) are not in SSA form, so we have to figure out where to put the phi's ourself. For this, we use the predecessor set information from nir_block. (We could perhaps use NIR's dominance frontier information to help with this?) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: a4xx encodes larger immed offsetRob Clark2015-06-211-0/+1
| | | | | | | Without this, negative branch/jump offsets look like very large positive offsets. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move inputs/outputs to shaderRob Clark2015-06-211-18/+13
| | | | | | | | | These belong in the shader, rather than the block. Mostly a lot of churn and nothing too interesting. But splitting this out from the rest of ir3_block reshuffling to cut down the noise in the later patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/ra: use register_allocateRob Clark2015-06-211-3/+32
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: introduce ir3_compiler objectRob Clark2015-06-211-1/+3
| | | | | | | | Right now, just provides a cleaner way to get at the gpu-id, given the separation between compiler and context. But we will need this also to hold the reg-set for new register allocation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove tgsi f/eRob Clark2015-06-211-1/+0
| | | | | | Also remove ir3_flatten which was only used by tgsi f/e. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: convert to priority queueRob Clark2015-06-211-0/+3
| | | | | | | | Use a more standard priority-queue based scheduling algo. It is simpler and will make things easier once we have multiple basic blocks and flow control. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use standard list implementationRob Clark2015-06-211-8/+7
| | | | | | | | | | Use standard list_head double-linked list and related iterators, helpers, etc, rather than weird combo of instruction array and next pointers depending on stage. Now block has an instrs_list. In certain stages where we want to remove and re-add to the blocks list we just use list_replace() to copy the list to a new list_head. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop dot graph dumpingRob Clark2015-06-211-7/+3
| | | | | | | | At least for now.. right now the instruction and instruction list printing should suffice, and the re-working of ir3_block would require a lot of changes in that code. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: more builder helpersRob Clark2015-06-211-0/+6
| | | | | | | | Use ir3_MOV() builder in a couple of spots, rather than open-coding the instruction construction. Also add ir3_NOP() builder and use that instead of open coding. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: UBO supportRob Clark2015-04-171-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move out helperRob Clark2015-04-171-0/+23
| | | | | | We'll also want it in NIR f/e for implementing UBO support. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: simplify emit_tex()Rob Clark2015-04-111-0/+28
| | | | | | | | Just build up arrays for src0/src1, and use create_collect().. Also add back missing .3d flag for 3d/cube textures. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/cp: support to swap mad src'sRob Clark2015-04-111-2/+2
| | | | | | | | | | | | | | | | For a normal MAD (ie. not MADSH), if first source is gpr and second source is const, we can swap the first two sources to avoid needing a mov instruction. This gives back the biggest advantage TGSI f/e had over NIR f/e for common shaders, since TGSI f/e had this logic in the f/e. Note that doing this in copy-prop step has the advantage that it will also work for cases like: MOV TEMP[b], CONST[x] MAD TEMP[d], TEMP[a], TEMP[b], TEMP[c] Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle const/immed/abs/neg in cpRob Clark2015-04-051-0/+6
| | | | | | | | | | | | | Be smarter about propagating copies from const or immed, or with abs/neg modifiers. Also, realize that absneg.s and absneg.f are really "fancy" mov instructions. This opens up the possibility to remove more copies. It helps the TGSI frontend a bit, but will be really needed for the NIR f/e which builds everything up in SSA form (ie. will *always* insert a mov from const or immediate). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split float/int abs/negRob Clark2015-04-051-8/+153
| | | | | | | | | | | | Even though in the end, they map to the same bits, the backend will need to be able to differentiate float abs/neg vs integer abs/neg. Rather than making the backend figure it out based on instruction opcode (which when combined with mov/absneg instructions, can be awkward), just split out different flags for each so the frontend can signal it's intentions more clearly. Also, since (neg) for bitwise op's is actually a bitwise- not, split it out into bnot flag. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add ir3 builder helpersRob Clark2015-04-051-2/+157
| | | | | | | | Add helpers for constructing SSA forms of instructions. Only partial cat5/cat6 coverage.. but we can add stuff as needed. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: avoid scheduler deadlockRob Clark2015-03-151-0/+13
| | | | | | | | | | | Deadlock can occur if we schedule an address register write, yet some instructions which depend on that address register value also depend on other unscheduled instructions that depend on a different address register value. To solve this, before scheduling an address register write, ensure that all the other dependencies of the instructions which consume this address register are already scheduled. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: bit of cleanupRob Clark2015-03-151-2/+15
| | | | | | | | Add an array_insert() macro to simplify inserting into dynamically sized arrays, add a comment, and remove unused prototype inherited from the original freedreno.git/fdre-a3xx test code, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: relative dstRob Clark2015-03-081-0/+22
| | | | | | | | | To simplify RA, assign arrays that are written to first. Since enough dependency information is in the graph to preserve order of reads and writes of array, so all SSA names for the array collapse into one, just assign the entire thing by array-id. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop deref nodesRob Clark2015-03-081-16/+19
| | | | | | | | | | | | | | | | | | | | | The meta-deref instruction doesn't really do what we need for relative destination. Instead, since each instruction can reference at most a single address value, track the dependency on the address register via instr->address. This lets us express the dependency regardless of whether it is used for dst and/or src. The foreach_ssa_src{_n} iterator macros now also iterates the address register so, at least in SSA form, the address register behaves as an additional virtual src to the instruction. Which is pretty much what we want, as far as scheduling/etc. TODO: For now, the foreach_src{_n} iterators are unchanged. We could wrap the address in an ir3_register and make the foreach_src_{_n} iterators behave the same way. But that seems unnecessary at this point, since we mainly care about the address dependency when in SSA form. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: helpful iterator macrosRob Clark2015-03-081-0/+34
| | | | | | | | | I remembered that we are using c99.. which makes some sugary iterator macros easier. So introduce iterator macros to iterate all src registers and all SSA src instructions. The _n variants also return the src #, since there are a handful of places that need this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle flat bypass for a4xxRob Clark2015-03-031-0/+6
| | | | | | | | | | | We may not need this for later a4xx patchlevels, but we do at least need this for patchlevel 0. Bypass bary.f for fetching varyings when flat shading is needed (rather than configure via cmdstream). This requires a special dummy bary.f w/ (ei) flag to signal to scheduler when all varyings are consumed. And requires shader variants based on rasterizer flatshade state to handle TGSI_INTERPOLATE_COLOR. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add support for memory (cat6) instructionsRob Clark2015-03-031-3/+5
| | | | | | | Scheduled basically the same as texture (cat5) instructions, using (sy) flag for synchronization. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: start on indirect gpr readsRob Clark2015-01-071-1/+4
| | | | | | | | | | | | | | Handle TEMP[ADDR[]] src registers by generating a fanin to group array elements, similarly to how texture fetch instructions work. NOTE: For all the scalar instructions generated for a single tgsi vector operation which uses an array src (or possibly even uses the same array as multiple srcs), re-use the same fanin node. Since a vector operation operates on all components at the same time, it should never see more than one version of the same array. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: make reg array dynamicRob Clark2015-01-071-3/+6
| | | | | | | | | To use fanin's to group registers in an array, we can potentially have a much larger array of registers. Rather than continuing to bump up the array size, just make it dynamically allocated when the instruction is created. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: simplify RARob Clark2015-01-071-14/+62
| | | | | | | | | | | | | | | | | | | | | | Group inputs/outputs, in addition to fanin/fanout, as they must also exist in sequential scalar registers. This lets us simplify RA by working in terms of neighbor groups. NOTE: has the slight problem that it can't optimize out mov's for things like: MOV OUT[n], IN[m] To avoid this, instead of trying to figure out what mov's we can eliminate, we first remove all mov's prior to grouping, and then re-insert mov's as needed while grouping inputs/outputs/fanins. Eventually we'd prefer the frontend to not insert extra mov's in the first place (so we don't have to bother removing them). This is the plan for an eventual NIR based frontend, so separate out the instr grouping (which will still be needed for NIR frontend) from the mov elimination (which won't). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: regmask support for relative addrRob Clark2015-01-071-16/+50
| | | | | | | | For temp arrays, a 32bit mask won't be sufficient.. but otoh we don't need to support an arbitrary mask. So for this case use a simple size field rather than a bitmask. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop instr_clone() stuffRob Clark2015-01-071-0/+3
| | | | | | | Unnecessary and overly complicated. And gets in the way for temp arrays (TEMP[ADDR[]]). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out legalize passRob Clark2014-12-231-1/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: ra debugRob Clark2014-12-231-3/+5
| | | | | | Some compile time RA debug Signed-off-by: Rob Clark <[email protected]>
* freedreno: add adreno 420 supportRob Clark2014-11-151-1/+1
| | | | | | | | Very initial support. Basic stuff working (es2gears, es2tri, and maybe about half of glmark2). Expect broken stuff. Still missing: mem->gmem (restore), queries, mipmaps (blob segfaults!), hw binning, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: consider instruction neighbors in cpRob Clark2014-10-251-0/+13
| | | | | | | | | | | | | | | | | Fanin (merge) nodes require it's srcs to be "adjacent" in consecutive scalar registers. Keep track of instruction neighbors in copy- propagation step and avoid eliminating mov's which would cause an instruction to need multiple distinct left and/or right neighbors. This lets us not fall on our face when we encounter things like: 1: MOV TEMP[2], IN[0].xyzw 2: TEX OUT[0].xy, TEMP[2], SAMP[0], SHADOW2D 3: MOV TEMP[2].xy, IN[0].yxzz 4: TEX OUT[0].zw, TEMP[2], SAMP[0], SHADOW2D 5: END Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: standalone compiler updates for ir3testRob Clark2014-10-251-0/+1
| | | | | | | | | | | | | | | In order to test compiler changes more easily, spit out the assembled shader with some header information so that we can know about inputs/outputs more easily. See: git://people.freedesktop.org/~robclark/ir3test In ir3test we have a big collection of tgsi shaders and reference ir3_compiler outputs. When making compiler changes, regenerate the compiler outputs and feed to ir3test to compare the new vs reference shader. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix potential gpu lockup with killRob Clark2014-10-201-0/+10
| | | | | | | | It seems like the hardware is unhappy if we execute a kill instruction prior to last input (ei). Probably the shader thread stops executing and the end-input flag is never set. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: large const supportRob Clark2014-10-151-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix lockups with lame FRAG shadersRob Clark2014-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Shaders like: FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0], LOCAL IMM[0] FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: TEX TEMP[0], IN[0].xyyy, SAMP[0], 2D 1: MOV OUT[0], IMM[0].xyxx 2: END cause unhappyness. They have an IN[], but once this is compiled the useless TEX instruction goes away. Leaving a varying that is never fetched, which makes the hw unhappy. In the process fix a signed vs unsigned compare. If the vertex shader has max_reg=-1, MAX2() vs an unsigned would not give the desired result. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add TXD support and expose ARB_shader_texture_lodIlia Mirkin2014-10-021-4/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: detect scheduler failRob Clark2014-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | There are some cases where the scheduler can get itself into impossible situations, by scheduling the wrong write to pred or addr register first. (Ie. it could end up being unable to schedule any instruction if some instruction which depends on the current addr/reg value also depends on another addr/reg value.) To solve this we'd need to be able to insert extra mov instructions (which would also help when register assignment gets into impossible situations). To do that, we'd need to move the nop padding from sched into legalize. But to start with, just detect when we get into an impossible situation and bail, rather than sitting forever in an infinite loop. This way it will at least fall back to the old compiler, which might even work if you are lucky. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out shader compiler from a3xxRob Clark2014-07-251-0/+480
Move the bits we want to share between generations from fd3_program to ir3_shader. So overall structure is: fdN_shader_stateobj -> ir3_shader -> ir3_shader_variant -> ir3 |- ... \- ir3_shader_variant -> ir3 So the ir3_shader becomes the topmost generation neutral object, which manages the set of variants each of which generates, compiles, and assembles it's own ir. There is a bit of additional renaming to s/fd3_compiler/ir3_compiler/, etc. Keep the split between the gallium level stateobj and the shader helper object because it might be a good idea to pre-compute some generation specific register values (ie. anything that is independent of linking). Signed-off-by: Rob Clark <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 01:26:07 +0000