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* freedreno/ir3: Remove unused half precision shader key flag.Eric Anholt2020-05-011-2/+0
| | | | | | | The code using it was removed in 4af86bd0b933 ("freedreno/ir3: remove half-precision output") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
* freedreno: Rename "is_blit" to "is_discard_blit"Eric Anholt2020-03-301-1/+1
| | | | | | | It's about the special case of an overwrite of a level meaning we can discard old batch contents. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
* freedreno: Rename vp and fp to vs and fs in fd_program_stateobjKristian H. Kristensen2019-09-251-2/+2
| | | | | | | | We're using vs and fs now, and adding hs, ds and gs soon. It's confusing enough that we have both DS/TCS and HS/TES. At least for VS and FS there doesn't have to be multiple names. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: move binning_pass out of shader variant keyRob Clark2018-10-171-3/+3
| | | | | | | | | | | Prep work for a following patch, that introduces a cache to map from program state (all shader stages) plus variant key to pre-baked hw state (which could be emit'd via CP_SET_DRAW_STATE, for example). To do that, we really want the variant key to be immutable, and to treat the binning pass shader as an extra shader stage, rather than as a VS variant. Signed-off-by: Rob Clark <[email protected]>
* freedreno: Remove the Emacs mode linesNeil Roberts2018-10-171-2/+0
| | | | | | | | | | | | | | | These are not necessary because the corresponding settings are set via the .dir-locals.el file anyway. Most of them were missing a ‘:’ after “tab-width” which was making Emacs display an annoying warning whenever you open the file. This patch was made with: sed -ri '/-\*- mode:/,/^$/d' \ $(find src/gallium/{drivers,winsys} -name \*.\[ch\] \ -exec grep -l -- '-\*- mode:' {} \+) Signed-off-by: Rob Clark <[email protected]>
* freedreno: register usage queriesRob Clark2018-07-181-1/+6
| | | | | | | Avg number of (half) regs per draw, so we can corrolate fps dips to shader register usage. Signed-off-by: Rob Clark <[email protected]>
* gallium: remove pipe_index_buffer and set_index_bufferMarek Olšák2017-05-101-6/+7
| | | | | | | | | | | | | | pipe_draw_info::indexed is replaced with index_size. index_size == 0 means non-indexed. Instead of pipe_index_buffer::offset, pipe_draw_info::start is used. For indexed indirect draws, pipe_draw_info::start is added to the indirect start. This is the only case when "start" affects indirect draws. pipe_draw_info::index is a union. Use either index::resource or index::user depending on the value of pipe_draw_info::has_user_indices. v2: fixes for nine, svga
* freedreno: refactor dirty state handlingRob Clark2017-04-181-3/+5
| | | | | | | | In particular, move per-shader-stage info out to a seperate array of enum's indexed by shader stage. This will make it easier to add more shader stages as well as new per-stage state (like SSBOs). Signed-off-by: Rob Clark <[email protected]>
* freedreno: add helper to mark all state cleanRob Clark2017-04-181-0/+2
| | | | | | | | Note that this involves juggling around a bit when we emit and clear texture state. So split out from the patch that adds the helper to set all state dirty. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: refactor out helpers for comparing shader keysRob Clark2017-04-181-28/+4
| | | | | | | | | | | | Each of the ir3 users has *basically* the same logic for comparing the previous and current shader key, to see which, if any, shader state needs to be marked dirty due to shader variant change. The difference between gen's was just that some lowering flags never get set on certain generations. But it doesn't really hurt to include the extra checks (because both keys would have false). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx+a4xx: fix clip-plane lowering stateRob Clark2016-10-071-0/+3
| | | | | | | If enabled clip-planes have changed, we need to mark program state dirty. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: use generic clear pathRob Clark2016-08-161-214/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx+a4xx: move common VBOs to fd_contextRob Clark2016-08-131-4/+2
| | | | | | | | These are the same for a3xx and later. (a2xx could probably use them too, but due to limited hw support and ancient downstream kernels, it isn't so easy to test.) Signed-off-by: Rob Clark <[email protected]>
* freedreno: move needs_wfi into batchRob Clark2016-07-301-3/+3
| | | | | | | This is also used in gmem code, which executes from the "bottom half" (ie. from the flush_queue worker thread), so it cannot be in fd_context. Signed-off-by: Rob Clark <[email protected]>
* freedreno: move more batch related tracking to fd_batchRob Clark2016-07-301-6/+5
| | | | | | | | | | | | | | | | To flush batches out of order, the gmem code needs to not depend on state from fd_context (since that may apply to a more recent batch). So this all moves into batch. The one exception is the gmem/pipe/tile state itself. But this is only used from gmem code (and batches are flushed serially). The alternative would be having to re-calculate GMEM layout on every batch, even if the dimensions of the render targets are the same. Note: This opens up the possibility of pushing gmem/submit into a helper thread. Signed-off-by: Rob Clark <[email protected]>
* freedreno: introduce fd_batchRob Clark2016-07-301-14/+16
| | | | | | | | | | | | | | | | | | | Introduce the batch object, to track a batch/submit's worth of ringbuffers and other bookkeeping. In this first step, just move the ringbuffers into batch, since that is mostly uninteresting churn. For now there is just a single batch at a time. Note that one outcome of this change is that rb's are allocated/freed on each use. But the expectation is that the bo pool in libdrm_freedreno will save us the GEM bo alloc/free which was the initial reason to implement a rb pool in gallium. The purpose of the batch is to eventually facilitate out-of-order rendering, with batches associated to framebuffer state, and tracking the dependencies on other batches. Signed-off-by: Rob Clark <[email protected]>
* freedreno: allow ctx->draw_vbo to failRob Clark2016-05-041-13/+16
| | | | | | | Pretty much only happens if shader variant compile fails. But in this case, if we haven't emitted cmdstream, we don't want to set needs_flush. Signed-off-by: Rob Clark <[email protected]>
* freedreno: move shader-stage dirty bits to global dirty flagRob Clark2016-05-041-9/+7
| | | | | | | | | | | This was always a bit overly complicated, and had some issues (like ctx->prog.dirty not getting reset at the end of the batch). It also required some special hacks to avoid resetting dirty state on binning pass. So just move it all into ctx->dirty (leaving some free bits for future shader stages), and make FD_DIRTY_PROG just be the union of all FD_SHADER_DIRTY_*. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add debug callback to emitRob Clark2016-04-301-0/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle color clamp variant ourselvesRob Clark2016-04-301-0/+8
| | | | | | | | | Now that there is a pass to do this in NIR, lets just use that and manage the variants ourself, rather than letting state-tracker do it. This way, mesa/st will precompile shaders without requiring ST_DEBUG=precompile (which requires a debug build). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: better workaround for astc+srgbRob Clark2016-04-241-3/+8
| | | | | | | | | | | | | | | This *seems* like a hw bug, and maybe only applies to certain a4xx variants/revisions. But setting the SRGB bit in sampler view state (texconst0) causes invalid alpha for ASTC textures. Work around this setting up a second texture state and using that to sample alpha separately. This way, srgb->linear conversion happens in hw *prior* to interpolation. This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb* Signed-off-by: Rob Clark <[email protected]>
* Revert "freedreno/a4xx: lower srgb in shader for astc textures"Rob Clark2016-04-241-8/+3
| | | | | | Better workaround in the following patch. This reverts commit 899bd63acefd49a668e11c42d2ad92fa55aa157d.
* freedreno/a4xx: lower srgb in shader for astc texturesRob Clark2016-04-191-3/+8
| | | | | | | | | | | | | | This *seems* like a hw bug, and maybe only applies to certain a4xx variants/revisions. But setting the SRGB bit in sampler view state (texconst0) causes invalid alpha for ASTC textures. Work around this by doing the srgb->linear conversion in the shader instead. This fixes 392 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb* (The remaining fails seem to be a bug w/ ASTC + linear filtering, also possibly a420.0 specific.) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: rasterizer_discard supportRob Clark2016-04-131-0/+17
| | | | | | | | | | | | | | | | | This one is slightly annoying, since trying to write RBRC from draw would clobber values set in the tiling/gmem code. We could do command- stream patching for RBRC, as is done on a3xx. Although since it seems to be a rarely used feature, it is easier just to do RMW to set/clear the bit. Fixes dEQP-GLES3.functional.rasterizer_discard.basic.write_depth_triangles and related tests. a3xx still needs the same feature, although there it probably makes more sense to take advantage of the existing cmdstream patching which is required for RBRC for other reasons. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: hw binningRob Clark2016-03-131-0/+39
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: move where we deal w/ binning FSRob Clark2016-03-131-0/+1
| | | | | | | Move where we pick dummy FS for binning pass, so the whole driver sees the same dummy/no-op FS stage. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: logic op handlingIlia Mirkin2015-11-201-2/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx+a4xx: fix GL_POINTS lockup w/ GLESRob Clark2015-11-181-0/+8
| | | | | | | | point_size_per_vertex is always TRUE for GLES, causing us to configure the hw as if gl_PointSize was written, even if it was not. Which makes for grumpy hw. Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove unnecessary null checksRob Clark2015-10-241-6/+6
| | | | | | | | According to piglit/xonotic/neverball/stc, blend/rasterize/zsa state will always be bound (never null). And the null checks were in- consistent anyways, so remove them. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: wire up ucp supportRob Clark2015-09-171-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: point-size and spritelist fixesRob Clark2015-08-121-0/+3
| | | | | | | | | a4xx needs similar treatment as 995f55a6 Also fixup a few point-size and vpsrepl issues and drop fix_blit_fp() hack previously needed for mem2gmem. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: MRT supportRob Clark2015-08-041-20/+16
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: small bit of cleanup about max rendertargetsRob Clark2015-08-041-1/+1
| | | | | | | | We hard-coded 4 or 8 as the max in various places. Switch it all to a define since the limit will go up with a4xx (and maybe even again in the future?) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move emit_const to ir3Rob Clark2015-07-271-1/+1
| | | | | | | | | | | | | | | Details of the cmdstream packets are different between a3xx and a4xx, but the logic about the layout of const registers is the same, as that is dictated by the ir3 shader compiler. So rather than duplicating logic that is tightly coupled to ir3 between a3xx and a4xx, move this into ir3 and use per-generation callbacks for to build the cmdstream packets. This should make it easier to pass additional const regs (such as for transform feedback). And it also keeps the layout internal to ir3 in case we want to make the layout more dynamic some day. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix crash in fail pathRob Clark2015-06-301-0/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove int sampler shader variantsRob Clark2015-06-211-6/+2
| | | | | | | | We get this information from NIR (which gets it from sview decl in tgsi when translating from tgsi), so no need to maintain shader variants for this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: wire up integer texture samplingRob Clark2015-04-221-2/+6
| | | | | | | Similar to a3xx, the compiler needs to know the return type of the sam, etc, instructions. Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove alpha key from ir3_shaderIlia Mirkin2015-04-021-4/+1
| | | | | | | This complication is unnecessary and makes MRTs more complicated and likely to generate tons of variants. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: handle flat bypass for a4xxRob Clark2015-03-031-1/+4
| | | | | | | | | | | We may not need this for later a4xx patchlevels, but we do at least need this for patchlevel 0. Bypass bary.f for fetching varyings when flat shading is needed (rather than configure via cmdstream). This requires a special dummy bary.f w/ (ei) flag to signal to scheduler when all varyings are consumed. And requires shader variants based on rasterizer flatshade state to handle TGSI_INTERPOLATE_COLOR. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: handle index_bias (i.e. base_vertex)Rob Clark2015-02-241-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: pass number of instances to drawRob Clark2015-02-241-1/+1
| | | | | | | a4xx has it's own draw packet, so needs equivalent update to what a3xx already got. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fd4_util -> fd4_formatRob Clark2014-12-041-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: stencil fixesRob Clark2014-11-301-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add render target format to fd4_emitRob Clark2014-11-301-1/+4
| | | | | | This lets us move emitting SP_FS_MRT_REG back to fd4_program_emit. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add adreno 420 supportRob Clark2014-11-151-0/+326
Very initial support. Basic stuff working (es2gears, es2tri, and maybe about half of glmark2). Expect broken stuff. Still missing: mem->gmem (restore), queries, mipmaps (blob segfaults!), hw binning, etc. Signed-off-by: Rob Clark <[email protected]>
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