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* gallium: plumb context priority through to driverRob Clark2017-12-191-0/+4
| | | | | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Andres Rodriguez <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* gallium/docs: document behavior of set_sample_mask()Brian Paul2017-12-131-1/+4
| | | | | | | | The sample mask is used even if msaa is not explicity enabled when we have a framebuffer with multisampled surfaces. That's DX behavior and what the Radeon drivers do. Not sure about other drivers at this point. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add hw atomic buffer binding API.Dave Airlie2017-11-101-0/+8
| | | | | | | | | | | | This API binds atomic buffers for all bound shaders (as per the GL semantics). This is needed to support cross shader hw atomic counters. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium/tgsi: start adding hw atomics (v3.2)Dave Airlie2017-11-101-3/+30
| | | | | | | | | | | | | | | | | | | | | This adds support for a hw atomic counters to TGSI. A new register file for storing atomic counters is added, along with a new atomic counter semantic, along with docs for both. v2: drop semantic, move hw counter to backend, Ilia pointed out SSO would have busted my plan, and he was right. v3: drop BUFFER decls. (Marek) v3.1: minor fixups for whitespace, set ureg error if we overflow the hw atomic limits. (nha) v3.2: fix some docs inconsistencies (Ilia) Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: add CAPs to support HW atomic counters. (v3)Dave Airlie2017-11-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This looks like an evergreen specific feature, but with atomic counters AMD have hw specific counters they use instead of operating on buffers directly. These are separate to the buffer atomics, so require different limits and code paths. I've left the CAP for atomic type extensible in case someone else has a variant on this sort of thing (freedreno maybe?) and needs to change it. This adds all the CAPs required to add support for those atomic counters, along with a related CAP for limiting the number of output resources. I'd like to land this and the st patch then I can start to upstream the evergreen support for these and other GL4.x features. v2: drop the ATOMIC_COUNTER_MODE cap, just use the return from the HW counters. If 0 we use the current mode. v3: fix some rebase errors (Gert Wollny) Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: add PIPE_FLUSH_{TOP,BOTTOM}_OF_PIPE bitsNicolai Hähnle2017-11-091-0/+14
| | | | | | | | | | | | | | | | These bits are intended to be used by the ddebug hang detection and are named in analogy to the Vulkan stage bits (and the corresponding Radeon pipeline event). Hang detection needs fences on the granularity of individual commands, which nothing else really covers. The closest alternative would have been PIPE_QUERY_GPU_FINISHED, but (a) queries are a per-context object and we really want a per-screen object, (b) queries don't offer a wait with timeout, and (c) in any case, PIPE_QUERY_GPU_FINISHED is meant to imply that GPU caches are flushed, which the new bits explicitly aren't. Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_FLUSH_ASYNC and PIPE_FLUSH_HINT_FINISHNicolai Hähnle2017-11-091-0/+9
| | | | | | Also document some subtleties of pipe_context::flush. Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSETMarek Olšák2017-11-061-0/+4
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* gallium: add cap for driver specified max combined shader resources.Dave Airlie2017-11-011-1/+3
| | | | | | | | Some hw (evergreen) has a limit on how many combined (images/buffers/mrts) a fragment shader can access. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.Eric Anholt2017-10-101-0/+3
| | | | | | | | | | | | | | | | Because vc4 can control the order that tiles are rasterized in, we can use it to implement overlapping blits using normal drawing and GL_ARB_texture_barrier, as long as we can tell the kernel what order to render the tiles in. This commit introduces the core gallium support, vc4 changes will follow. v2: Fix on the simulator. v3: Add the cap (disabled) to other drivers, add rst docs for the cap. v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS v5: Drop vc4 changes from this commit, for clarity. Reviewed-by: Nicolai Hähnle <[email protected]> (v3)
* gallium: add PIPE_CAP_TGSI_ANY_REG_AS_ADDRESSMarek Olšák2017-10-061-0/+2
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi: add docs for some existing pack opcodesMarek Olšák2017-10-061-3/+21
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add new LOD opcodeRoland Scheidegger2017-09-301-0/+12
| | | | | | | | | | The operation performed is all the same as LODQ, but with the usual differences between dx10 and GL texture opcodes, that is separate resource and sampler indices (plus result swizzling, and setting z/w channels to zero). Reviewed-by: Jose Fonseca <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* gallium: add LDEXP TGSI instruction and corresponding capNicolai Hähnle2017-09-292-0/+13
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* tgsi: clarify the semantics of DFRACEXPNicolai Hähnle2017-09-291-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The status quo is quite the mess: 1. tgsi_exec will do a per-channel computation, and store the dst[0] result (significand) correctly for each channel. The dst[1] result (exponent) will be written to the first bit set in the writemask. So per-component calculation only works partially. 2. r600 will only do a single computation. It will replicate the exponent but not the significand. 3. The docs pretend that there's per-component calculation, but even get dst[0] and dst[1] confused. 4. Luckily, st_glsl_to_tgsi only ever emits single-component instructions, and kind-of assumes that everything is replicated, generating this for the dvec4 case: DFRACEXP TEMP[0].xy, TEMP[1].x, CONST[0][0].xyxy DFRACEXP TEMP[0].zw, TEMP[1].y, CONST[0][0].zwzw DFRACEXP TEMP[2].xy, TEMP[1].z, CONST[0][1].xyxy DFRACEXP TEMP[2].zw, TEMP[1].w, CONST[0][1].zwzw Settle on the simplest behavior, which is single-component calculation with replication, document it, and adjust tgsi_exec and r600. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* tgsi: fix the documentation of DLDEXPNicolai Hähnle2017-09-291-1/+1
| | | | | | | | | Sourcing the exponent for the zw destination pair from Z is consistent with both tgsi_exec and gallivm. In practice, st_glsl_to_tgsi always generates per-channel instructions anyway. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/docs: add reference links for resource_create methodGwan-gyeong Mun2017-09-281-2/+2
| | | | | | | It adds reference links for arguments usage and bind of resource_create(). Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/docs: fix a reference link for get_paramfGwan-gyeong Mun2017-09-281-1/+1
| | | | | | | | Previous get_paramf links same as get_param. It changes the reference link to PIPE_CAPF_* Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Add PIPE_SHADER_CAP_INT64_ATOMICSJan Vesely2017-09-211-0/+1
| | | | | | | Denotes availability of 64bit int atomic instructions Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: Add PIPE_SHADER_CAP_FP16Jan Vesely2017-09-181-0/+2
| | | | | | | | | Denotes native half precision float operations capability v2: PIPE_CAP_HALFS -> PIPE_SHADER_CAP_FP16 fix indentation Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVENicolai Hähnle2017-09-181-0/+6
| | | | | | | | | | | | | | | | | To be able to properly distinguish between GL_ANY_SAMPLES_PASSED and GL_ANY_SAMPLES_PASSED_CONSERVATIVE. This patch goes through all drivers, having them treat the two query types identically, except: 1. radeon incorrectly enabled conservative mode on PIPE_QUERY_OCCLUSION_PREDICATE. We now do it correctly, only on PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE. 2. st/mesa uses the new query type. Fixes dEQP-GLES31.functional.fbo.no_attachments.* Reviewed-by: Marek Olšák <[email protected]>
* gallium: introduce PIPE_CAP_LOAD_CONSTBUFTimothy Arceri2017-09-151-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: all drivers should accept two-dimensional constant buffer indexingNicolai Hähnle2017-09-041-8/+3
| | | | | | | | | Most older drivers seem to just ignore the Dimension setting, so virtually no changes should be needed. Acked-by: Roland Scheidegger <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* gallium/docs: Fix an inequality sign of TGSI_SEMANTIC_SUBGROUP_LT_MASKGwan-gyeong Mun2017-08-281-1/+1
| | | | | | | | | | | | | | A previous expression presents same as TGSI_SEMANTIC_SUBGROUP_GT_MASK. It fixes a direction of an inequality for TGSI_SEMANTIC_SUBGROUP_LT_MASK. before: bit index > TGSI_SEMANTIC_SUBGROUP_INVOCATION after: bit index < TGSI_SEMANTIC_SUBGROUP_INVOCATION Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: fix a typoGwan-gyeong Mun2017-08-281-1/+1
| | | | | Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: Fix the math formula of U2I64Gwan-gyeong Mun2017-08-231-2/+2
| | | | | | | | | | | | | before: dst.xy = (uint64_t) src0.x dst.zw = (uint64_t) src0.y after: dst.xy = (int64_t) src0.x dst.zw = (int64_t) src0.y Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: Add missing word "Not"Gwan-gyeong Mun2017-08-231-1/+1
| | | | | Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: remove TGSI opcode SCSMarek Olšák2017-08-221-13/+0
| | | | | | | use COS+SIN instead. Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Jose Fonseca <[email protected]>
* gallium: remove TGSI opcode BREAKCMarek Olšák2017-08-221-15/+1
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: remove TGSI opcode XPDMarek Olšák2017-08-221-13/+1
| | | | | | use MUL+MAD+MOV instead. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: remove TGSI opcode DPHMarek Olšák2017-08-221-10/+1
| | | | | | use DP4 or DP3 + ADD. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: remove TGSI opcode DP2AMarek Olšák2017-08-221-13/+0
| | | | | | use DP3 instead. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: remove TGSI_OPCODE_CALLNZMarek Olšák2017-08-221-13/+0
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: remove TGSI FENCE opcodesMarek Olšák2017-08-221-30/+0
| | | | | | use MEMBAR instead Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZMarek Olšák2017-08-221-50/+0
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/docs: remove old llvmpipe TODOTimothy Arceri2017-08-221-14/+0
| | | | | | | Features are already covered by features.txt like all the other drivers. Reviewed-by: Eric Engestrom <[email protected]>
* gallium/docs: add more info about TXF and MSAA texturesBrian Paul2017-08-031-1/+3
| | | | | | | If the texture is multisampled, the coord.w component indicates which sample to fetch. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/docs: document automatic per-sample FS executionBrian Paul2017-08-031-0/+6
| | | | | | | | | Both the GLSL 4.00 specs and DX10.1 specs specify that if a fragment shader uses the sample ID or sample position inputs, the shader is automatically run at per sample frequency. Document that expectation for gallium fragment shaders. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: introduce PIPE_CAP_MEMOBJTimothy Arceri2017-08-031-0/+1
| | | | | | | | | | | | | | This can be used to guard support for EXT_memory_object and related extensions. v2: update gallium docs v3 (Timothy Arceri): - add cap to nv50 Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE and corresponding capNicolai Hähnle2017-08-022-2/+15
| | | | | | | | v2: rename cap to PIPE_CAP_QUERY_SO_OVERFLOW and be a bit more explicit in the documentation Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_NIR_SAMPLERS_AS_DEREFNicolai Hähnle2017-07-311-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/docs: add precise instruction modifierKarol Herbst2017-07-211-1/+10
| | | | | | | | v4: add comment about intermediate rounding step to MAD Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/docs: document that TXF is used with PIPE_BUFFER resourcesBrian Paul2017-06-301-1/+2
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/docs: clarify that samplers are not used with PIPE_BUFFER resourcesBrian Paul2017-06-301-0/+8
| | | | | | | | Commit 8aba778fa2cd98a0b5a7429d3c5057778a0c808c "st/mesa: don't set sampler states for TBOs" changed how texture buffer objects are handled. Document the new convention. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/docs: improve docs for SAMPLE_POS, SAMPLE_INFO, TXQS, MSAA semanticsBrian Paul2017-06-161-11/+47
| | | | | | | | | | | | | | | | | | | | | For the SAMPLE_POS and SAMPLE_INFO opcodes, clarify resource vs. render target queries, range of postion values, swizzling, etc. We basically follow the DX10.1 conventions. For the TXQS opcode and TGSI_SEMANTIC_SAMPLEID, clarify return value and type. For the TGSI_SEMANTIC_SAMPLEPOS system value, clarify the range of positions returned. v2: use 'undef' for unused vector components. Use (0.5, 0.5, undef, undef) for sample pos when MSAA not applicable. v3: Add note that OPCODE_SAMPLE_INFO, OPCODE_SAMPLE_POS are not used yet and the information is subject to change. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: add ARB_bindless_texture interfaceSamuel Pitoiset2017-06-141-0/+20
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_BINDLESS_TEXTURESamuel Pitoiset2017-06-141-0/+2
| | | | | | | | | Whether bindless texture operations are supported by the underlying driver. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: clarify TGSI_SEMANTIC_SAMPLEMASK, againBrian Paul2017-06-131-4/+11
| | | | | | | | | I've since discovered the fragment shader sample mask system value (which corresponds to gl_SampleMaskIn). v2: It's a system value, not a shader input. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: clarify gen_name/get_vendor/get_device_vendor behaviorMarek Olšák2017-06-121-0/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi: clarify TGSI_SEMANTIC_SAMPLEMASK documentationBrian Paul2017-06-091-2/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
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