aboutsummaryrefslogtreecommitdiffstats
path: root/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
Commit message (Collapse)AuthorAgeFilesLines
* tgsi/ureg: Add missing some missing opcodes opcode_tmp.hEric Anholt2015-02-061-0/+4
| | | | | | I wanted all of these for NIR-to-TGSI. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium: Drop the unused CND opcode.Eric Anholt2014-11-241-1/+0
| | | | | | Nothing in the tree generates it. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop unused BRA opcode.Eric Anholt2014-11-241-1/+0
| | | | | | Never generated, and implemented in only nvfx vertprog. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop the unused SFL/STR opcodes.Eric Anholt2014-11-241-2/+0
| | | | | | Nothing generated them. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop the unused RFL opcode.Eric Anholt2014-11-241-1/+0
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop unused X2D opcode.Eric Anholt2014-11-241-1/+0
| | | | | | Nothing in the tree generates it. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop the unused ARA opcode.Eric Anholt2014-11-241-1/+0
| | | | | | | | Nothing in the tree generated it. v2: Only drop ARA, not ARR as well. Reviewed-by: Jose Fonseca <[email protected]> (v2)
* gallium: Drop the unused RCC opcode.Eric Anholt2014-11-241-1/+0
| | | | | | Nothing in the tree generated it. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Drop the NRM and NRM4 opcodes.Eric Anholt2014-11-241-2/+0
| | | | | | | They weren't generated in tree, and as far as I know all hardware had to lower it to a DP, RSQ, MUL. Reviewed-by: Jose Fonseca <[email protected]>
* tgsi/ureg: add ureg_UARL shortcut (v2)Christoph Bumiller2014-11-181-0/+1
| | | | | | | | v2: moved in in same order as in p_shader_tokens (thanks Brian) Acked-by: Jose Fonseca <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: David Heidelberg <[email protected]>
* util/tgsi: Fix ureg_EMIT/ENDPRIM prototype.José Fonseca2014-07-151-2/+2
| | | | | | | | 0cbefc1bea703378381afff946e30c27a21f191d added a source argument to EMIT/ENDPRIM, but it did not update tgsi_ureg accordingly, causing all users of ureg_EMIT/ENDPRIM to fail at runtime with an assertion failure. Trivial.
* s/Tungsten Graphics/VMware/José Fonseca2014-01-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/[email protected]/[email protected]/ s/[email protected]/[email protected]/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\[email protected]/[email protected]/g s/keithw\[email protected]/[email protected]/g s/[email protected]/[email protected]/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/[email protected]/[email protected]/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <[email protected]>
* gallium: Add support for 32x32 muls with 64 bit resultsZack Rusin2013-10-091-0/+3
| | | | | | | | | | | | | | The code introduces two new 32bit integer multiplication opcodes which can be used to produce correct 64 bit results. GLSL, OpenCL and D3D10+ require them. We use two seperate opcodes, because they match the behavior of GLSL and OpenCL, are a lot easier to add than a single opcode with multiple destinations and because there's not much (any) difference wrt code-generation. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* tgsi: implement new float comparison instructions returning integer masksRoland Scheidegger2013-08-131-0/+4
| | | | | | | | Also while here add a bunch of other forgotten (integer) instructions to tgsi_util_get_inst_usage_mask() (which isn't used for much except optimizing away unused input components), though it may still be incomplete. Reviewed-by: Zack Rusin <[email protected]>
* tgsi: add ucmp to the list of opcodesZack Rusin2013-08-021-0/+1
| | | | | | | | | we forgot to add ucmp to the list of opcodes, so it was never generated for ureg. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* tgsi: rename the TGSI fragment kill opcodesBrian Paul2013-07-121-2/+2
| | | | | | | | | | | | | | | | | | | | | TGSI_OPCODE_KIL and KILP had confusing names. The former was conditional kill (if any src component < 0). The later was unconditional kill. At one time KILP was supposed to work with NV-style condition codes/predicates but we never had that in TGSI. This patch renames both opcodes: TGSI_OPCODE_KIL -> KILL_IF (kill if src.xyzw < 0) TGSI_OPCODE_KILP -> KILL (unconditional kill) Note: I didn't just transpose the opcode names to help ensure that I didn't miss updating any code anywhere. I believe I've updated all the relevant code and comments but I'm not 100% sure that some drivers had this right in the first place. For example, the radeon driver might have llvm.AMDGPU.kill and llvm.AMDGPU.kilp mixed up. Driver authors should review their code. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: Disambiguate TGSI_OPCODE_IF.José Fonseca2013-04-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TGSI_OPCODE_IF condition had two possible interpretations: - src.x != 0.0f - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was false either for vertex and fragment shaders - gallivm/llvmpipe - postprocess - vl state tracker - vega state tracker - most old drivers - old internal state trackers - many graw examples - src.x != 0U - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was true for both vertex and fragment shaders - tgsi_exec/softpipe - r600 - radeonsi - nv50 And drivers that use draw module also were a mess (because Mesa would emit float IFs, but draw module supports native integers so it would interpret IF arg as integers...) This sort of works if the source argument is limited to float +0.0f or +1.0f, integer 0, but would fail if source is float -0.0f, or integer in the float NaN range. It could also fail if source is integer 1, and hardware flushes denormalized numbers to zero. But with this change there are now two opcodes, IF and UIF, with clear meaning. Drivers that do not support native integers do not need to worry about UIF. However, for backwards compatibility with old state trackers and examples, it is advisable that native integer capable drivers also support the float IF opcode. I tried to implement this for r600 and radeonsi based on the surrounding code. I couldn't do this for nouveau, so I just shunted IF/UIF together, which matches the current behavior. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> v2: - Incorporate Roland's feedback. - Fix r600_shader.c merge conflict. - Fix typo in radeon, spotted by Michel Dänzer. - Incorporte Christoph Bumiller's patch to handle TGSI_OPCODE_IF(float) properly in nv50/ir.
* gallium: Eliminate TGSI_OPCODE_IFC.José Fonseca2013-04-171-1/+0
| | | | | | Never used or implemented. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm/tgsi: fix issues with sample opcodesRoland Scheidegger2013-02-161-9/+29
| | | | | | | | We need to encode them as Texture instructions since the NumOffsets field is encoded there. However, we don't encode the actual target in there, this is derived from the sampler view src later. Reviewed-by: Jose Fonseca <[email protected]>
* gallium: fix tgsi SAMPLE_L opcode to use separate source for explicit lodRoland Scheidegger2013-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | It looks like using coord.w as explicit lod value is a mistake, most likely because some dx10 docs had it specified that way. Seems this was changed though: http://msdn.microsoft.com/en-us/library/windows/desktop/hh447229%28v=vs.85%29.aspx - let's just hope it doesn't depend on runtime build version or something. Not only would this need translation (so go against the stated goal these opcodes should be close to dx10 semantics) but it would prevent usage of this opcode with cube arrays, which is apparently possible: http://msdn.microsoft.com/en-us/library/windows/desktop/bb509699%28v=vs.85%29.aspx (Note not only does this show cube arrays using explicit lod, but also the confusion with this opcode: it lists an explicit lod parameter value, but then states last component of location is used as lod). (For "true" hw drivers, only nv50 had code to handle it, and it appears the code was already right for the new semantics, though fix up the seemingly wrong c/d arguments while there.) v2: fix comment, separate out other changes. Reviewed-by: Jose Fonseca <[email protected]>
* tgsi: add support for new SQRT opcodeBrian Paul2013-02-041-0/+1
|
* gallium/tgsi: Split sampler views from shader resources.Francisco Jerez2012-05-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit splits the current concept of resource into "sampler views" and "shader resources": "Sampler views" are textures or buffers that are bound to a given shader stage and can be read from in conjunction with a sampler object. They are analogous to OpenGL texture objects or Direct3D SRVs. "Shader resources" are textures or buffers that can be read and written from a shader. There's no support for floating point coordinates, address wrap modes or filtering, and, unlike sampler views, shader resources are global for the whole graphics pipeline. They are analogous to OpenGL image objects (as in ARB_shader_image_load_store) or Direct3D UAVs. Most hardware is likely to implement shader resources and sampler views as separate objects, so, having the distinction at the API level simplifies things slightly for the driver. This patch introduces the SVIEW register file with a declaration token and syntax analogous to the already existing RES register file. After this change, the SAMPLE_* opcodes no longer accept a resource as input, but rather a SVIEW object. To preserve the functionality of reading from a sampler view with integer coordinates, the SAMPLE_I(_MS) opcodes are introduced which are similar to LOAD(_MS) but take a SVIEW register instead of a RES register as argument.
* gallium: implement modern sampling schemeZack Rusin2011-01-241-0/+17
| | | | | | | | | | | largely a merge of the previously discussed origin/gallium-resource-sampling but updated. the idea is to allow arbitrary binding of resources, the way opencl, new gl versions and dx10+ require, i.e. DCL RES[0], 2D, FLOAT LOAD DST[0], SRC[0], RES[0] SAMPLE DST[0], SRC[0], RES[0], SAMP[0]
* tgsi: add switch/case opcodes to tgsi_opcode_tmp.hLuca Barbieri2010-09-201-0/+4
|
* tgsi: Drop BGNFOR, ENDFOR, REP, and ENDREP opcodes.José Fonseca2010-04-271-4/+0
|
* gallium: Add UMOD TGSI opcode.Michal Krol2010-01-051-0/+1
| | | | Either that or have UDIV have two destination operands.
* tgsi: Implement new integer opcodes.Michal Krol2010-01-051-1/+21
| | | | | Update interpreter and ureg. Also, get rid of SHR -- it's actually an alias for ISHR.
* gallium: remove the swizzling parts of ExtSwizzleKeith Whitwell2009-10-231-1/+0
| | | | | | | | | These haven't been used by the mesa state tracker since the conversion to tgsi_ureg, and it seems that none of the other state trackers are using it either. This helps simplify one of the biggest suprises when starting off with TGSI shaders.
* gallium: remove noise opcodesKeith Whitwell2009-10-231-4/+0
| | | | | | | | | | | Provide a dummy implementation in the GL state tracker (move 0.5 to the destination regs). At some point, a motivated person could add a better implementation of noise. Currently not even the nvidia binary drivers do anything more than this. In any case, the place to do this is in the GL state tracker, not the poor driver.
* tgsi: remove redundant CND0 opcodeKeith Whitwell2009-09-011-1/+0
| | | | Can be implemented with CMP src2, src1, src0
* tgsi: add tgsi_ureg, a simplified tgsi shader builderKeith Whitwell2009-08-131-0/+173
This is modelled on the nice & easy-to-use facilities we had for building shaders in mesa, eg. in texenvprogram.c and friends. Key points include pass-by-value register structs that can be manipulated in a functional style, eg: negate(swizzle(reg, X,X,X,X)) and per-opcode instruction functions, eg: emit_MOV( p, writemask(dst, 0x1), negate(src)); and similar. Additionally, the interface allows mixed emit of instructions and decls, which are sorted out internally to obey TGSI ordering. Immediates may be emitted at any time and are scanned against existing immediates to try and reduce redundancy. Not all TGSI functionality is accessible through this interface, but most or all of what mesa uses should be.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 03:13:58 +0000