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* util: Move gallium's PIPE_FORMAT utils to /util/format/Eric Anholt2019-11-141-1/+1
* freedreno/ir3: remove unused parameterRob Clark2019-11-121-4/+4
* freedreno/ir3: legalize cleanupsRob Clark2019-11-121-1/+7
* freedreno/ir3: fix gpu hang with pre-fs-tex-fetchRob Clark2019-11-122-10/+32
* freedreno/ir3: only tex instructions have wrmaskRob Clark2019-11-121-6/+3
* freedreno/ir3: re-work shader inputs/outputsRob Clark2019-11-125-270/+192
* freedreno/ir3: simplify creating sysval inputsRob Clark2019-11-121-90/+58
* freedreno/ir3: remove first-vertex sysvalRob Clark2019-11-121-1/+0
* freedreno/ir3: helper to print ir if debug enabledRob Clark2019-11-122-28/+16
* freedreno/ir3: show input/output wrmask's in disasmRob Clark2019-11-121-2/+9
* freedreno/ir3: add input/output iteratorsRob Clark2019-11-1211-63/+49
* freedreno/ir3: remove impossible conditionRob Clark2019-11-121-3/+0
* freedreno/ir3: rename fanin/fanout to collect/splitRob Clark2019-11-1210-44/+48
* freedreno/ir3: remove half-precision outputRob Clark2019-11-121-30/+0
* freedreno/ir3: fix valgrind complaint with STLWRob Clark2019-11-121-1/+1
* freedreno: add Adreno 640 IDJonathan Marek2019-11-111-0/+1
* freedreno/ir3: also track # of nops for shader-dbRob Clark2019-11-092-0/+4
* freedreno/ir3: sync disasm changes from envytoolsRob Clark2019-11-092-24/+94
* freedreno/ir3: remove obsolete commentRob Clark2019-11-091-4/+0
* freedreno/ir3/ra: remove ir print after livein/outRob Clark2019-11-091-1/+0
* freedreno/ir3/ra: move regs_count==0 checkRob Clark2019-11-091-9/+2
* freedreno/ir3: ir3_print tweaksRob Clark2019-11-092-47/+102
* freedreno/ir3: use SSA flag on dest register tooRob Clark2019-11-094-45/+48
* freedreno/ir3: split pre-coloring to it's own functionRob Clark2019-11-091-3/+12
* freedreno/ir3: Use regid() helper when setting up precolor regsKristian H. Kristensen2019-11-071-4/+4
* freedreno/a6xx: Program state for tessellation stagesKristian H. Kristensen2019-11-071-0/+5
* freedreno/ir3: Allocate const space for tessellation parametersKristian H. Kristensen2019-11-071-0/+7
* freedreno/ir3: Pre-color TCS header and primitive ID inputsKristian H. Kristensen2019-11-071-2/+12
* freedreno/ir3: Don't assume binning shader is always VSKristian H. Kristensen2019-11-071-2/+2
* freedreno/ir3: Setup inputs and outputs for tessellation stagesKristian H. Kristensen2019-11-071-7/+52
* freedreno/ir3: Implement TCS synchronization intrinsicsKristian H. Kristensen2019-11-071-0/+33
* freedreno/ir3: Implement tess coord intrinsicKristian H. Kristensen2019-11-071-0/+12
* freedreno/ir3: End TES with chsh when using GSKristian H. Kristensen2019-11-071-1/+3
* freedreno/ir3: Add new synchronization opcodesKristian H. Kristensen2019-11-075-1/+15
* freedreno/ir3: Extend geometry lowering pass to handle tessellationKristian H. Kristensen2019-11-073-8/+520
* freedreno/ir3: Add tessellation field to shader keyKristian H. Kristensen2019-11-072-1/+34
* freedreno/ir3: Use imul24 in offset calculationsKristian H. Kristensen2019-11-071-2/+2
* freedreno/ir3: Add ir3 intrinsics for tessellationKristian H. Kristensen2019-11-074-0/+26
* freedreno/ir3: Add load and store intrinsics for global ioKristian H. Kristensen2019-11-071-0/+49
* freedreno/a6xx: Add register offset for STG/LDGKristian H. Kristensen2019-11-075-9/+64
* freedreno/a6x: Rename z/s formatsKristian H. Kristensen2019-11-073-10/+10
* freedreno/a6xx: Fix layered texture type enumKristian H. Kristensen2019-11-071-3/+4
* freedreno/a6xx: Clear sysmem with CP_BLITKristian H. Kristensen2019-11-071-0/+4
* freedreno/registers: Add comments about primitive countersKristian H. Kristensen2019-11-071-12/+10
* freedreno/registers: Move SP_PRIMITIVE_CNTL and SP_VS_VPC_DSTKristian H. Kristensen2019-11-071-28/+28
* freedreno/registers: Fix typoKristian H. Kristensen2019-11-071-1/+1
* meson: move the generic symbols check arguments to a common variableEric Engestrom2019-11-051-1/+1
* meson: add variable to control the symbols checksEric Engestrom2019-11-051-1/+1
* util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIANDylan Baker2019-11-051-1/+1
* util/u_endian: set PIPE_ARCH_*_ENDIAN to 1Dylan Baker2019-11-051-1/+1
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