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* freedreno/ir3: Fix operand order for DSX/DSYKristian H. Kristensen2019-03-251-0/+15
| | | | | | | | | | Most cat5 instructions are constructed using ir3_SAM, which uses regs[1] for the (sampler, tex) src. Not DSX/DSY though, so we look up src1 and src2 differently for those two. Fixes: 1dffb089 ("freedreno/ir3: fix sam.s2en encoding") Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/ir3: Track whether shader needs derivativesKristian H. Kristensen2019-03-254-3/+9
| | | | | | | | | | | | | In 1088b788 ("freedreno/ir3: find # of samplers from uniform vars") we started counting number of samplers based on the uniform vars instead of number of cat5 instructions. We used the number of samplers to determine whether to enable derivatives, but when we only use derivatives and no samplers, that now breaks. Track whether we need derivatives explicitly and use that to enable the state. Fixes: 1088b788 ("freedreno/ir3: find # of samplers from uniform vars") Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* spirv,nir: lower frexp_exp/frexp_sig inside a new NIR passSamuel Pitoiset2019-03-221-0/+1
| | | | | | | | | | This lowering isn't needed for RADV because AMDGCN has two instructions. It will be disabled for RADV in an upcoming series. While we are at it, factorize a little bit. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* freedreno/ir3: disable early-z for SSBO/image writesRob Clark2019-03-221-0/+12
| | | | | | | | | | | Fixes: dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_stencil dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_stencil_fbo Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rename has_kill to no_earlyzRob Clark2019-03-223-4/+4
| | | | | | | There are other cases where we need to disable early-z, like image writes. So rename to something more generic. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: dynamic UBO indexing vs 64b pointersRob Clark2019-03-211-2/+2
| | | | | | | Fixes dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_fragment and similar things with multiple UBOs Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix bit_countRob Clark2019-03-211-2/+23
| | | | | | | | | Seems like it can only work 16b at a time. Fixes dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.* TODO need to check if this limitation applies to a3xx as well. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: additional loweringRob Clark2019-03-211-0/+6
| | | | | | | | | For some things that show up when we expose higher glsl TODO check blob traces to see if we have instructions for some of this? I guess we don't but worth a check.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: optimize sam.s2en to samRob Clark2019-03-213-6/+36
| | | | | | | Detect when sampler/texture idx are immediate and switch to non s2en encoding. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: enable indirect tex/samp (sam.s2en)Rob Clark2019-03-212-22/+73
| | | | | | | | | | For now it uses indirect for everything. The next step is for the ir3_cp pass to detect the case that tex and samp idx are immediate and convert the sam instruction back to the non .s2en variant. But doing that in a following patch so we can shake out the bugs with .s2en more easily. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: find # of samplers from uniform varsRob Clark2019-03-213-13/+13
| | | | | | | When we have indirect samplers, we cannot tell the max sampler referenced. Instead just refer to the number of sampler uniforms. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix regmask for merged regsRob Clark2019-03-212-3/+13
| | | | | | | | On a6xx+ with half-regs conflicting with full-regs, the legalize pass needs to set appropriate sync bits, such as (sy), on writes to full regs that conflict with half regs, and visa-versa. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix sam.s2en encodingRob Clark2019-03-212-9/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix sam.s2en decodingRob Clark2019-03-211-3/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/ra: fix half-class conflictsRob Clark2019-03-211-7/+14
| | | | | | | | | | | | On a6xx, half-regs conflict with full-regs. But we were only setting up conflicts for the first class (ie. scalar, but not hvec2/hvec3/hvec4), resulting in higher half-reg classes getting assigned to regs that overwrite full-regs. Noticed while trying to enable indirect-sampler (sam.s2en) which uses an hvec2 argument to pass the sampler/tex index. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3 better cat6 encoding detectionRob Clark2019-03-212-8/+24
| | | | | | | These two bits seem to be a better way to detect which encoding we are looking at. Signed-off-by: Rob Clark <[email protected]>
* anv,radv,turnip: Lower TG4 offsets with nir_lower_texJason Ekstrand2019-03-211-0/+1
| | | | | | v2: turn on for turnip as well (Karol Herbst) Reviewed-by: Karol Herbst <[email protected]>
* freedreno/ir3/a6xx: fix ssbo comp_swapRob Clark2019-03-201-1/+1
| | | | | | | One line left out of the conversion to ir3 ssbo intrinsics on a6xx. Fixes: 2e4525883f0 ir3/compiler: Enable lower_io_offsets pass and handle new SSBO intrinsics Signed-off-by: Rob Clark <[email protected]>
* turnip: Deconflict vk_format_table regenerationBas Nieuwenhuizen2019-03-161-3/+3
| | | | | | | | | | | | Avoids src/freedreno/vulkan/meson.build:42:0: ERROR: Tried to create target "vk_format_table.c", but a target of that name already exists. when building both radv and turnip. Fixes: 26380b3a9f8 "turnip: Add driver skeleton (v2)" Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* turnip: Fix GCC compiles.Bas Nieuwenhuizen2019-03-161-6/+3
| | | | | | | | | | Apparently GCC does not consider static const variables to be integer constants, and hence the array size and the static assert result in compile failures. Fixes: 4b9f967cd1a "turnip: add a more complete format table" Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3/cp: fix ldib bugRob Clark2019-03-151-0/+6
| | | | | | | Something that we didn't hit earlier because of the extra shr.b Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* ir3/lower_io_offsets: Try propagate SSBO's SHR into a previous shift instructionEduardo Lima Mitev2019-03-131-4/+94
| | | | | | | | | | | | | | | While we lack value range tracking, this patch tries to 'manually' propogate the division by 4 to calculate SSBO element-offset, into a possible previous shift operation (shift left or right); checking that it is safe to do so. This should help in cases like ie. when accessing a field in an array of structs, where the offset is likely defined as base plus a multiplication by a struct or array element size. See dEQP test 'dEQP-GLES31.functional.ssbo.atomic.xor.highp_uint' for an example of a shader that benefits from this. Reviewed-by: Rob Clark <[email protected]>
* ir3/compiler: Enable lower_io_offsets pass and handle new SSBO intrinsicsEduardo Lima Mitev2019-03-134-60/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These intrinsics have the offset in dwords already computed in the last source, so the change here is basically using that instead of emitting the ir3_SHR to divide the byte-offset by 4. The improvement in shader stats is significant, of up to ~15% in instruction count in some cases. Tested only on a5xx. shader-db is unfortunately not very useful here because shaders that use SSBO require GLSL versions that are not supported by freedreno yet. For examples, most Khronos CTS tests under 'dEQP-GLES31.functional.ssbo.*' are helped. A random case: dEQP-GLES31.functional.ssbo.layout.2_level_array.packed.row_major_mat3x2 with current master: ; CL prog 14/1: 1252 instructions, 0 half, 48 full ; 8 const, 8 constlen ; 61 (ss), 43 (sy) with the SSBO dword-offset moved to NIR: ; CL prog 14/1: 1053 instructions, 0 half, 45 full ; 7 const, 7 constlen ; 34 (ss), 73 (sy) The SHR previously emitted for every single SSBO instruction disappears in most cases, and the dword-offset ends up embedded in the STGB instruction as immediate in many cases as well. There are also a few of those tests that are currently failing on register allocation, that start to pass as a result of reducing the pressure. At least these, probably more: dEQP-GLES31.functional.ssbo.layout.random.unsized_arrays.24 dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6 dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.17 dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays.14 dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.5 dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.7 No regressions observed with relevant CTS and piglit tests. Reviewed-by: Rob Clark <[email protected]>
* ir3/nir: Add a new pass 'ir3_nir_lower_io_offsets'Eduardo Lima Mitev2019-03-134-0/+217
| | | | | | | | | | | | | | | | | | | | This NIR->NIR pass implements offset computations that are currently done on the IR3 backend compiler, to give NIR a better chance of optimizing them. For now, it supports lowering the dword-offset computation for SSBO instructions. It will take an SSBO intrinsic and replace it with the new ir3-specific version that adds an extra source. That source will hold the SSA value resulting from inserting a division by 4 (an SHR op) of the original byte-offset source already provided by NIR in one of the intrinsic sources. Note that on a6xx the original byte-offset is not needed, so we could potentially replace that source instead of adding a new one. But to keep things simple and consistent we always add the new source and a6xx will just ignore the original one. Reviewed-by: Rob Clark <[email protected]>
* turnip: preliminary support for Wayland WSIChia-I Wu2019-03-116-1/+358
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* turnip: preliminary support for tu_GetImageSubresourceLayoutChia-I Wu2019-03-111-5/+11
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* turnip: Use Vulkan 1.1 names instead of KHRChad Versace2019-03-118-100/+100
| | | | | | | That is, drop KHR from all tokens that were promoted to Vulkan 1.1. The consistency makes ctags more useful (it now jumps directly to the real definitions in vulkan_core.h instead of the typedefs); and it makes the code slightly less verbose.
* turnip: preliminary support for tu_CmdDrawChia-I Wu2019-03-111-0/+83
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* turnip: preliminary support for draw state bindingChia-I Wu2019-03-112-4/+357
| | | | | This adds support for tu_CmdBindPipeline, tu_CmdBindVertexBuffers, etc.
* turnip: add draw_cs to tu_cmd_bufferChia-I Wu2019-03-112-3/+21
| | | | It will hold draw commands.
* turnip: parse VkPipelineVertexInputStateCreateInfoChia-I Wu2019-03-112-0/+134
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* turnip: parse VkPipelineShaderStageCreateInfoChia-I Wu2019-03-112-0/+602
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* turnip: compile VkPipelineShaderStageCreateInfoChia-I Wu2019-03-112-0/+143
| | | | Compile all shaders and upload the binaries to a BO.
* turnip: preliminary support for shader modulesChia-I Wu2019-03-115-5/+411
| | | | | | Save SPIR-V in tu_shader_module. Tranlation to NIR happens in tu_shader_create, and compilation to binary code happens in tu_shader_compile. Both will be called during pipeline creation.
* turnip: parse VkPipeline{Multisample,ColorBlend}StateCreateInfoChia-I Wu2019-03-113-0/+355
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* turnip: parse VkPipelineDepthStencilStateCreateInfoChia-I Wu2019-03-112-2/+204
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* turnip: parse VkPipelineRasterizationStateCreateInfoChia-I Wu2019-03-112-0/+128
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* turnip: parse VkPipelineViewportStateCreateInfoChia-I Wu2019-03-112-1/+130
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* turnip: parse VkPipelineInputAssemblyStateCreateInfoChia-I Wu2019-03-112-0/+49
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* turnip: parse VkPipelineDynamicStateCreateInfoChia-I Wu2019-03-111-0/+46
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* turnip: create a less dummy pipelineChia-I Wu2019-03-112-30/+109
| | | | Still dummy, but at least it is created from tu_pipeline_builder.
* turnip: simplify tu_cs sub-streams usageChia-I Wu2019-03-112-7/+12
| | | | | | Let tu_cs_begin_sub_stream imply tu_cs_reserve_space, and tu_cs_end_sub_stream imply tu_cs_sanity_check. Callers are no longer required to call them (but can still do if they choose to).
* turnip: fix tu_cs sub-streamsChia-I Wu2019-03-111-1/+5
| | | | | Update cs->start in tu_cs_end_sub_stream. Otherwise, the entry would include commands from all prior sub-streams.
* turnip: tu_cs_emit_arrayChia-I Wu2019-03-111-0/+11
| | | | | | Array version of tu_cs_emit. Useful for updating multiple consecutive array-like registers, or loading a shader binary with SS6_DIRECT.
* turnip: add tu_cs_discard_entriesChia-I Wu2019-03-111-0/+11
| | | | | | We will start a draw IB at the beginning of a subpass and consume it at the end of the subpass. With tu_cs_discard_entries, we can reuse the same tu_cs for all subpasses.
* turnip: more/better asserts for tu_csChia-I Wu2019-03-111-2/+4
| | | | | | | | Asserting (cur < end) in tu_cs_emit catches much less programming errors comparing to asserting (cur < reserved_end). We should never write more commands than what we have reserved. Assert IB is non-empty and sane in tu_cs_emit_ib.
* turnip: use 32-bit offset in tu_cs_entryChia-I Wu2019-03-112-2/+6
| | | | We don't support nor expect BOs to be that big in tu_cs.
* turnip: mark IBs for dumpingChia-I Wu2019-03-112-3/+4
| | | | Includes IBs in kernel cmdbuf dumps.
* turnip: use the platform defines in vk.xml instead of hard-coding themEric Engestrom2019-03-111-4/+7
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* turnip: Add todo for copies.Bas Nieuwenhuizen2019-03-111-0/+7
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