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* tu: Rewrite variable loweringConnor Abbott2020-07-061-12/+166
| | | | | | | | | | Don't lower to offsets, instead use nir_lower_explicit_io here and use actual pointers for UBO's and SSBO's. This makes KHR_variable_pointers trivial. This also fixes asserts with shared variables, which are now supposed to be lowered with nir_lower_explicit_io. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5684>
* freedreno: Only call nir_lower_io on shader_in/outJason Ekstrand2020-07-061-2/+2
| | | | | | | | | | Gallium drivers should never see nir_var_uniform because gallium lowers regular uniforms to a UBO. No GL driver should ever see either nir_var_mem_shared because that's lowered in GLSL IR. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5418>
* ir3: mark ucp_enables as allowed values on all keysIlia Mirkin2020-07-061-0/+2
| | | | | | | | Both vertex and fragment shaders need to have the lowering. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5751>
* a4xx: add noperspective interpolation supportIlia Mirkin2020-07-061-6/+11
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5753>
* freedreno/regs: document SS6_UBO state srcJonathan Marek2020-07-061-0/+8
| | | | | | | Document this new a6xx_state_src value seen in A640/A650 tess traces. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5760>
* freedreno/fdperf: prefer render nodeRob Clark2020-07-061-1/+1
| | | | | | | | Avoid inadvertantly becoming master if fdperf happens to be the first thing to open the device. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5762>
* freedreno/fdperf: better compatible string matchingRob Clark2020-07-061-4/+32
| | | | | | | | | | | | | | | | Previously we would match the start of the compatible string, in a couple of cases, in order to match compatible strings like "qcom,adreno-630.2". But these cases would always list a more generic compatible (ie. "qcom,adreno") as a later choice. So if we parse all the compatible strings, we can do a more precise exact match. This avoids us accidentially matching on "qcom,adreno-smmu" and the hilarity that ensues. Fixes: 5a13507164a ("freedreno/perfcntrs: add fdperf") Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5762>
* freedreno/fdperf: fix print of base addressRob Clark2020-07-061-1/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5762>
* freedreno/ir3: fix/rework tess levelsJonathan Marek2020-07-062-153/+85
| | | | | | | | | | | | | | | | | | | | | | | | | The previous version assumes tess level outputs will only be written once in the shader, however its not possible to guarantee that. It also assumes all invocations will write all the levels, which is also not guaranteed. This is required to fix the "tesselation" and "terraintessellation" demos with turnip. The comment about nir_lower_io_to_temporaries in lower_tess_ctrl_block is removed because nir_lower_io_to_temporaries specifically skips TESS_CTRL shaders so the comment doesn't make sense. The split load for tess levels workaround is removed, the new version only has scalar access unless if ever gets vectorized. This sets NIR_COMPACT_ARRAYS cap to avoid the glsl tess vec lowering with gallium. It seems this will also disable "LowerCombinedClipCullDistance", which I'm not sure was needed or not. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5744>
* freedreno/layout: fix explicit layout offset not added to slice offsetJonathan Marek2020-07-061-1/+1
| | | | | | | | | | | | | Accidentally broke this when rebasing the offending commit. My use case with non-zero explicit offset is UV plane of UBWC NV12, and only the UBWC slice offset is used for the UBWC sampler, so I didn't catch it immediately. Fixes: d53dc6c37680eba8e8 ("freedreno/fdl6: rework layout code a bit (reduce linear align to 64 bytes)") Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5761>
* turnip: enable 420_UNORM formatsJonathan Marek2020-07-054-2/+67
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4600>
* turnip: support multi-image layoutsJonathan Marek2020-07-054-115/+200
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4600>
* turnip: clear_blit: pass aspect mask to setup functionJonathan Marek2020-07-051-109/+61
| | | | | | | Avoids having to duplicate logic to figure out the write mask on D24S8 Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4600>
* turnip: fix tess param bo size calculationJonathan Marek2020-07-043-43/+13
| | | | | | | | | | | ir3 already calculates the stride in the tess param bo, so use that instead of a incorrect calculation. The calculation of per_vertex_output_size / per_patch_output_size is wrong because it counts dwords instead of bytes, and what it counts for per_vertex_output_size is a per-patch size because the glsl type is already an array of # vertex/patch elements. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5743>
* turnip: vsc improvementsJonathan Marek2020-07-033-125/+109
| | | | | | | | | | | | | * Remove scratch_bo from cmdbuffer, use a device-global bo instead, which also includes border color (and eventually shaders for 3D blit path) * Use CP_SET_BIN_DATA5_OFFSET to allow setting VSC buffer addresses only once at the start of the cmdstream * Use scratch bo mechanism for a resizable VSC buffer * Use feedback from "vsc_draw_overflow" and "vsc_prim_overflow" values to increase the size of VSC buffer when beginning to record a new cmdbuffer Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5570>
* turnip: rework render_tiles loopJonathan Marek2020-07-031-38/+17
| | | | | | | | | | | Loop through pipes and then loop over the tiles in that pipe instead of looping over all tiles then having to calculate the pipe # and slot #. Mainly this avoids the hard to follow "config_get_tile" logic, but should also be a gain due to better use of cache with the VSC data. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5570>
* turnip: make tiling config part of framebuffer stateJonathan Marek2020-07-035-271/+215
| | | | | | | | | | | | | Compute the tiling config at framebuffer creation time. A framebuffer will b be re-used multiple times, so this will avoid having to re-calculate the tiling config every time a command buffer is recorded. The tiling config already couldn't use the render area's x1/y1 because of hw binning, this move makes it so the render area isn't used at all for the tiling config. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5570>
* tu,radv: fix potentially wrong offset of flexible array.Hyunjun Ko2020-07-031-6/+4
| | | | | | | v2. Remove redundant memset and make the expression simpler. Signed-off-by: Hyunjun Ko <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5703>
* freedreno/ir3: add support for INTERP_MODE_NOPERSPECTIVEJonathan Marek2020-07-011-21/+50
| | | | | | | | Check the interp mode and use SYSTEM_VALUE_BARYCENTRIC_LINEAR_* instead when it is INTERP_MODE_NOPERSPECTIVE. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5582>
* turnip: set missing bary sysvalsJonathan Marek2020-07-011-30/+43
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5582>
* freedreno/ir3: add generic get_barycentric()Jonathan Marek2020-07-013-28/+43
| | | | | | | This will be useful to support the missing barycentric sysvals. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5582>
* freedreno/registers: update varying-related registersJonathan Marek2020-07-015-29/+53
| | | | | | | | | | | Note: * a3xx change based on available register documentation * a4xx guesses (RB_RENDER_CONTROL2 bits especially) * a5xx change based on a6xx, these registers seem identical Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5582>
* turnip: enable depthBiasClampJonathan Marek2020-06-291-1/+1
| | | | | | | Passes at least dEQP-VK.dynamic_state.rs_state.depth_bias_clamp Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5678>
* turnip: enable largePointsJonathan Marek2020-06-291-3/+3
| | | | | | | Passes dEQP-VK.rasterization.primitive_size.points.point_size_* Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5678>
* freedreno/regs: add extra bits for UBWC array pitchJonathan Marek2020-06-291-2/+2
| | | | | | | | | | | This is not completely tested, but matches the max array pitch allowed by A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH. Note this still doesn't allow all image sizes, but it allows 16384x16384 cpp=4 images to work. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5678>
* freedreno/ir3: fix resinfo wrmaskJonathan Marek2020-06-281-1/+3
| | | | | | | | | | | resinfo always writes 3 components, which was not being taken into account Fixes these tests: dEQP-VK.renderpass.suballocation.attachment_sparse_filling.input_attachment_3 dEQP-VK.renderpass.suballocation.attachment_sparse_filling.input_attachment_7 Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5674>
* turnip: Put VK_KHR_external_fence_fd stubs backKristian H. Kristensen2020-06-261-0/+19
| | | | | | | | tu_ImportFenceFdKHR is used by tu_AcquireImageANDROID, which may or may not work, but let's at least keep things compiling until somebody has time to tie up the loose ends on the Android side. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5670>
* turnip: Properly return VK_DEVICE_LOST on queuesubmit failures.Eric Anholt2020-06-264-8/+59
| | | | | | The device lost support closely matches the anv code for the same. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>
* turnip: Fix error handling of DRM_MSM_GEM_INFO ioctls.Eric Anholt2020-06-261-5/+11
| | | | | | | | | | | drmCommandWriteRead gives us a -errno, and we only checked for -1 (-EPERM, incidentally). All the callers wanted 0 for errors, which they were getting by the fact that req.value was 0-initialized in our stack allocation (though this only works as long as the kernel doesn't return an error after setting req.value to something), and -EPERM not really being an answer we would expect from an ioctl at this stage in the driver. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>
* turnip: Do better TU_DEBUG=startup logging of drmGetDevices2() failure.Eric Anholt2020-06-261-2/+6
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>
* turnip: semaphore support.Bas Nieuwenhuizen2020-06-263-44/+289
| | | | | | | | | There is only one queue for now, so for non-shared semaphores, the implementation is basically a no-op. For shared semaphores, this always uses syncobjs. This depends on syncobj support in the msm kernel driver. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>
* freedreno/ir3: move nir finalization to after cache missRob Clark2020-06-262-7/+12
| | | | | | | | | In cases where every variant is a shader-cache-hit, we never need the post-finalize round of nir opt/lowering passes. So defer this until the first shader-cache-miss to avoid doing pointless work. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
* freedreno/ir3: disk-cache supportRob Clark2020-06-267-3/+270
| | | | | | | | | | | | Adds a shader disk-cache for ir3 shader variants. Note that builds with `-Dshader-cache=false` have no-op stubs with `disk_cache_create()` that returns NULL. Binning pass variants are serialized together with their draw-pass counterparts, due to shared const-state. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
* freedreno/ir3: build binning variant at same time as draw variantRob Clark2020-06-261-31/+68
| | | | | | | | | | | For shader-cache, we are going to want to serialize them together. Which is awkward if the two related variants are not compiled together. This also decouples allocation and compile, which will simplify adding shader-cache (which still needs to allocate, but can skip compile). Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
* freedreno/a6xx+ir3: stop generating pointless binning shadersRob Clark2020-06-262-1/+13
| | | | | | | | | | | | Currently we always do sysmem if there is tess. And for GS, the binning pass VS ends up identical to the draw pass VS, so no point in compiling it twice. (For GS what we should do someday is generate a binning pass GS, and possibly if we can do cross-stage linking opts, an optimized binning pass VS, but the required outputs would somehow have to end up in the shader variant key.) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
* freedreno/ir3: shuffle some variant fieldsRob Clark2020-06-261-11/+20
| | | | | | | | Just to group together the parts that will get serialized when we have shader disk-cache. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
* freedreno/ir3: add ir3_compiler_destroy()Rob Clark2020-06-263-3/+10
| | | | | | | | | Use ir3_compiler_destroy() rather than open-coding ralloc_free(). This will give us a place to add more compiler related cleanup code in the following patches. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
* freedreno/ir3: move finalize_nir to pscreen hookRob Clark2020-06-262-2/+2
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
* freedreno/ir3: add ir3_finalize_nir()Rob Clark2020-06-263-35/+48
| | | | | | | | | | | The next step is to hook this into pscreen->finalize_nir() so it can come before the state tracker's shader-caching. Unfortunately we still need to do lower_io after mesa/st, so that is split out into a post-finalize pass. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
* turnip: fix huge scissor min/max caseJonathan Marek2020-06-261-0/+9
| | | | | | | | | | | | Now that tu_cs_emit_regs is used for the scissor, it hits an assert when the scissor is too large. Fixes this dEQP test: dEQP-VK.draw.scissor.static_scissor_max_int32 Fixes: 9c0ae5704d654108fd36b ("turnip: fix empty scissor case") Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5655>
* turnip: fix VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURESJonathan Marek2020-06-261-15/+15
| | | | | | | | | | My attempt to be clever here backfired, it overwrites the pNext and stops the loop (causing deqp to fail to query extension features after that). Fixes: 62de79ac4492ac9e ("turnip: implement VK_KHR_shader_draw_parameters") Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5654>
* tu: Pass firstIndex directly to CP_DRAW_INDX_OFFSETConnor Abbott2020-06-262-5/+4
| | | | | | | | Saves some minor overhead, cleans things up a bit, and removes one more unknown. We now program the internal registers in the same way between direct/indirect draws. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
* freedreno/registers: Label firstIndex field in CP_DRAW_INDX_OFFSETConnor Abbott2020-06-261-0/+1
| | | | | | | Based on comparing the implementations of CP_DRAW_INDX_OFFSET and CP_DRAW_INDIRECT, this is what this field is for. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
* freedreno: On a5xx+ INDX_SIZE is MAX_INDICESConnor Abbott2020-06-261-2/+3
| | | | | | | | | This was already done correctly for the indirect variants, and turnip was setting the correct value, but it seems freedreno missed the change in the non-indirect variant. Also, fix a misspelling of "indices" and add a type to INDX_SIZE. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
* tu: Share constlen between different stages properlyConnor Abbott2020-06-261-2/+23
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
* ir3: Add ir3_trim_constlen()Connor Abbott2020-06-262-0/+71
| | | | | | | This provides the policy for how to handle reducing constlen for some stages. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
* ir3: Support variants with different constlen'sConnor Abbott2020-06-267-12/+83
| | | | | | | | This provides the mechanism for compiling variants with a reduced constlen. The next patch provides the policy for choosing which to reduce. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
* ir3: Include ir3_compiler from ir3_shaderConnor Abbott2020-06-267-7/+8
| | | | | | | I wanted to access the ir3_compiler from a small helper inside ir3_shader.h, which currently isn't possible. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
* ir3, freedreno: Round up constlen earlierConnor Abbott2020-06-263-4/+12
| | | | | | | Prevents problems when calculating whether we overflow the shared limit. Note that on a6xx, the macros handle the assert for us. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
* turnip: Add support for polygon fill modes.Eric Anholt2020-06-254-5/+25
| | | | | | Passes the new tests in dEQP-VK.rasterization.culling.* Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 05:10:50 +0000