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* freedreno/ir3: Add missing ir3_nir_lower_tex_prefetch.c to Android.mkMarijn Suijten2019-10-211-0/+1
* nir/lower_idiv: add new llvm-based pathRhys Perry2019-10-211-1/+1
* freedreno/ir3: handle imad24_ir3 case in UBO loweringRob Clark2019-10-181-2/+27
* freedreno/ir3: add imul24 opcodeRob Clark2019-10-181-0/+3
* freedreno/ir3: optimize immed 2nd src to madRob Clark2019-10-181-2/+11
* freedreno/ir3: add rule to generate imad24Rob Clark2019-10-181-0/+5
* nir: add nir_lower_amul passRob Clark2019-10-182-0/+4
* freedreno/ir3: Handle newly added opcode nir_op_imad24_ir3Eduardo Lima Mitev2019-10-181-0/+3
* freedreno/ir3: rename mul.s/mul.uRob Clark2019-10-185-12/+12
* freedreno/ir3: enable pre-fs texture fetch for a6xxRob Clark2019-10-181-0/+6
* turnip: add support for pre-fs texture fetchRob Clark2019-10-181-3/+21
* freedreno/ir3: Add support for texture sampling pre-dispatchHyunjun Ko2019-10-181-2/+73
* freedreno/ir3: Add a NIR pass to select tex instructions eligible for pre-fetchEduardo Lima Mitev2019-10-183-0/+199
* freedreno/ir3: force i/j pixel to r0.xRob Clark2019-10-181-0/+22
* freedreno/ir3: add pre-dispatch tex fetch to disasmRob Clark2019-10-181-0/+10
* freedreno/ir3: add dummy bary.f(ei) for pre-fs-fetchRob Clark2019-10-181-0/+19
* freedreno/ir3: fixup register footprint to account for prefetchRob Clark2019-10-181-0/+14
* freedreno/ir3: add meta instruction for pre-fs texture fetchRob Clark2019-10-186-3/+33
* freedreno/ir3: don't DCE ij_pix if used for pre-fs-texture-fetchRob Clark2019-10-183-6/+14
* freedreno/ir3: track sysval slot for inputsRob Clark2019-10-183-0/+12
* freedreno/ir3: remove unused ir3_instruction::inoutRob Clark2019-10-183-5/+0
* freedreno/ir3: Add data structures to support texture pre-fetchHyunjun Ko2019-10-181-0/+37
* freedreno: update registersRob Clark2019-10-182-2/+23
* freedreno/a6xx: Implement PIPE_QUERY_PRIMITIVES_GENERATED for GSKristian H. Kristensen2019-10-172-0/+34
* freedreno/ir3: End VS with CHMASK and CHSH in GS pipelinesKristian H. Kristensen2019-10-171-1/+18
* freedreno/ir3: Start GS with (ss) and (sy)Kristian H. Kristensen2019-10-171-0/+13
* freedreno/ir3: Pre-color GS header and primitive IDKristian H. Kristensen2019-10-171-0/+9
* freedreno/ir3: Setup ir3 inputs and outputs for GSKristian H. Kristensen2019-10-171-3/+64
* freedreno/ir3: Implement primitive layout intrinsicsKristian H. Kristensen2019-10-173-0/+31
* freedreno/ir3: Implement lowering passes for VS and GSKristian H. Kristensen2019-10-178-2/+496
* freedreno/ir3: Add has_gs flag to shader keyKristian H. Kristensen2019-10-171-0/+4
* freedreno/ir3: Add intrinsics that map to LDLW/STLWKristian H. Kristensen2019-10-171-0/+75
* freedreno/ir3: Add new LDLW/STLW instructionsKristian H. Kristensen2019-10-174-3/+8
* freedreno/ir3: Extend RA with mechanism for pre-coloring registersKristian H. Kristensen2019-10-173-50/+60
* freedreno/ir3: Use third register for offset for LDL and LDLVKristian H. Kristensen2019-10-174-12/+18
* freedreno/ir3: Add support for CHSH and CHMASK instructionsKristian H. Kristensen2019-10-172-1/+3
* freedreno/registers: Update with GS, HS and DS registersKristian H. Kristensen2019-10-174-9/+105
* nir: support feeding state to nir_lower_clip_[vg]sErik Faye-Lund2019-10-171-1/+1
* nir: support lowering clipdist to arraysErik Faye-Lund2019-10-171-2/+2
* turnip: more descriptor setsJonathan Marek2019-10-156-50/+250
* turnip: push constantsJonathan Marek2019-10-153-11/+50
* turnip: depth/stencilJonathan Marek2019-10-153-20/+95
* turnip: basic msaa workingJonathan Marek2019-10-154-20/+67
* turnip: improve CmdCopyImage and implement CmdBlitImageJonathan Marek2019-10-158-590/+526
* turnip: use nir_assign_io_var_locations instead of nir_assign_var_locationsJonathan Marek2019-10-151-6/+2
* turnip: add missing nir passesJonathan Marek2019-10-151-5/+50
* turnip: add code to lower indirect samplersJonathan Marek2019-10-151-14/+63
* turnip: fixup constsJonathan Marek2019-10-152-5/+6
* turnip: update some shader state bits from GL driverJonathan Marek2019-10-151-68/+80
* turnip: Emit clears of gmem using linear.Eric Anholt2019-10-151-1/+1
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