aboutsummaryrefslogtreecommitdiffstats
path: root/src/freedreno
Commit message (Collapse)AuthorAgeFilesLines
* freedreno/ir3: don't overwrite wrmask in ir3_SAMJonathan Marek2020-04-141-2/+2
| | | | | | | | | | Fixes (with other patches to allow these tests to run): dEQP-VK.ycbcr.query.size_lod.vertex.* Suggested-by: Rob Clark <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4557>
* freedreno/ir3: fix emit_tex_info split_destJonathan Marek2020-04-141-2/+1
| | | | | | | | | Fixes a "free(): invalid next size (fast)" error in: dEQP-VK.glsl.texture_functions.query.texturequerylevels.* Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4557>
* ir3: Fix txs with bindlessConnor Abbott2020-04-141-3/+3
| | | | | | | | | | | | I missed that this had a micro-optimization to assume that there was only ever one source, which is no longer valid for the bindless model since we now have a bindless handle source. Remove the optimization to fix assertion failures with turnip. Fixes e.g. dEQP-VK.glsl.texture_functions.query.texturesize.sampler2d_fixed_vertex Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4548>
* freedreno/ir3/ra: cleanup some leftoversRob Clark2020-04-131-6/+0
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: rename depth->dceRob Clark2020-04-137-68/+18
| | | | | | | | Since DCE is the only remaining function of this pass, after the pre-RA scheduler rewrite. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: better cleanup when removing unused instructionsRob Clark2020-04-134-10/+36
| | | | | | | | | | | | Do a better job of pruning when removing unused instructions, including cleaning up dangling false-deps. This introduces a new ssa src pointer iterator, which makes it easy to clear links without having to think about whether it is a normal ssa src or a false-dep. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3/ra: handle array case for SFU select_reg optRob Clark2020-04-131-3/+10
| | | | | | | | | | | The src of the SFU instruction could also be array/reg (non-SSA). Handle this case too. The postsched cp pass makes this scenario more likely. Fixes: cc82521de4e ("freedreno/ir3: round-robin RA") Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: add mov/cov statsRob Clark2020-04-133-4/+12
| | | | | | | | While not always avoidable, cov instructions are a useful thing to look at to see if we could fold into src. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3/postsched: avoid moving tex ahead of killRob Clark2020-04-131-0/+18
| | | | | | | | Add extra dependencies of tex/mem instructions on previous kill instructions to avoid moving them ahead of kills. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3/postsched: remove some leftoversRob Clark2020-04-131-9/+0
| | | | | | | These aren't used in postsched. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3/sched: awareness of partial livenessRob Clark2020-04-131-1/+44
| | | | | | | | | Realize that certain instructions make a vecN live, and account for this, in hopes of scheduling the remaining components of the vecN sooner. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: new pre-RA schedulerRob Clark2020-04-133-396/+426
| | | | | | | | | | | | This replaces the depth-first search scheduler with a more traditional ready-list scheduler. It primarily tries to reduce register pressure (number of live values), with the exception of trying to schedule kills as early as possible. (Earlier iterations of this scheduler had a tendency to push kills later, and in particular moving texture fetches which may not be necessary ahead of kills.) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: fix location of inserted mov'sRob Clark2020-04-131-1/+11
| | | | | | | | | | | If the group pass must insert a mov to resolve conflicts, avoid the mov appearing *after* the meta:collect whose src it is. The current pre-RA scheduler doesn't really care about the initial instruction order, but the new one will in some cases. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: simplify grouping passRob Clark2020-04-131-31/+18
| | | | | | | | Since bdf6b7018cedf95b554e21953d5a1935d3067ce7 the logic only needs to handle grouping collect srcs, So remove the now unnecessary indirection. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: make falsedep use's optionalRob Clark2020-04-133-4/+6
| | | | | | | | Add option when collecting uses to control whether they include falsedeps or not. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: spiff out disasm a bitRob Clark2020-04-131-5/+17
| | | | | | | | for verbose mode, print also the instruction "cycle" (which takes into account (rptN) and (nopN)) in addition to instruction offset. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/computerator: support bindless sampler instructionsJonathan Marek2020-04-132-1/+4
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4526>
* freedreno/computerator: support nop prefixJonathan Marek2020-04-132-1/+6
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4526>
* freedreno/ir3: CSE the up/downconversion of SEL's cond's size.Eric Anholt2020-04-133-7/+22
| | | | | | | | | | | | | | | | | Not many programs hit this, but if you were, say, selecting between vec4s, you'd convert the cond 4 times. instructions in affected programs: 2957 -> 2717 (-8.12%) nops in affected programs: 989 -> 899 (-9.10%) non-nops in affected programs: 1968 -> 1818 (-7.62%) dwords in affected programs: 3232 -> 2752 (-14.85%) last-baryf in affected programs: 102 -> 90 (-11.76%) full in affected programs: 5 -> 4 (-20.00%) sstall in affected programs: 329 -> 329 (0.00%) (ss) in affected programs: 86 -> 105 (22.09%) (sy) in affected programs: 14 -> 12 (-14.29%) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4516>
* freedreno/ir3: Stop doing b2n on the SEL condition.Eric Anholt2020-04-132-3/+11
| | | | | | | | | | | | | | | | | | SEL_B32 (and presumably B16) checks for 0 or nonzero in the condition (tested by just stuffing a uniform's value into it), so there's no need to do ir3_b2n() on it, or any preceding ir3_n2b(). instructions in affected programs: 664444 -> 659927 (-0.68%) nops in affected programs: 267898 -> 266312 (-0.59%) non-nops in affected programs: 420260 -> 417329 (-0.70%) dwords in affected programs: 144032 -> 137568 (-4.49%) last-baryf in affected programs: 10801 -> 10321 (-4.44%) full in affected programs: 2003 -> 2002 (-0.05%) sstall in affected programs: 76670 -> 77405 (0.96%) (ss) in affected programs: 4515 -> 4525 (0.22%) (sy) in affected programs: 612 -> 604 (-1.31%) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4516>
* freedreno: Fix leak of binning shader variants.Eric Anholt2020-04-101-0/+2
| | | | | | | | | | The v->binning variant is never added to shader->variants, so just free each one as we free the nonbinning variant. Noticed from drm-shim mode running out of open fds, since each bo ends up with an fd. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4502>
* freedreno/ir3: Fix sz vs class confusionKristian H. Kristensen2020-04-102-6/+24
| | | | | | | | Add bounds checking to make sure we don't silently access out of bounds again. Fixes: 90f7d12236c ("freedreno/ir3/ra: pick higher numbered scalars in first pass") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4503>
* tu: Implement descriptor set update templatesConnor Abbott2020-04-092-4/+125
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* tu: Add missing code for immutable samplersConnor Abbott2020-04-091-0/+20
| | | | | | Actually fill out the samplers, based on the radv implementation. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* tu: Emit CP_LOAD_STATE6 for descriptorsConnor Abbott2020-04-095-5/+304
| | | | | | | This restores the pre-loading of descriptor state, using the new SS6_BINDLESS method that allows us to pre-load bindless resources. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* tu: Switch to the bindless descriptor modelConnor Abbott2020-04-097-868/+673
| | | | | | | | | | | | | | | | | | | | | | | Under the bindless model, there are 5 "base" registers programmed with a 64-bit address, and sam/ldib/ldc and so on each specify a base register and an offset, in units of 16 dwords. The base registers correspond to descriptor sets in Vulkan. We allocate a buffer at descriptor set creation time, hopefully outside the main rendering loop, and then switching descriptor sets is just a matter of programming the base registers differently. Note, however, that some kinds of descriptors need to be patched at command recording time, in particular dynamic UBO's and SSBO's, which need to be patched at CmdBindDescriptorSets time, and input attachments which need to be patched at draw time based on the the pipeline that's bound. We reserve the fifth base register (which seems to be unused by the blob driver) for these, creating a descriptor set on-the-fly and combining all the dynamic descriptors from all the different descriptor sets. This way, we never have to copy the rest of the descriptor set at draw time like the blob seems to do. I mostly chose to do this because the infrastructure was already there in the form of dynamic_descriptors, and other drivers (at least radv) don't cheat either when implementing this. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* ir3: Rewrite UBO push analysis to support bindlessConnor Abbott2020-04-093-59/+107
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* ir3: Plumb through bindless supportConnor Abbott2020-04-0910-99/+520
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* ir3: LDC also has a destinationConnor Abbott2020-04-091-1/+1
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* ir3: Also don't propagate immediate offset with LDCConnor Abbott2020-04-091-3/+3
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* ir3: Plumb through support for a1.xConnor Abbott2020-04-0911-67/+164
| | | | | | | | This will need to be used in some cases for the upcoming bindless support, plus ldc.k instructions which push data from a UBO to const registers. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* ir3: Add bindless instruction encodingConnor Abbott2020-04-093-103/+277
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* freedreno/a6xx: Add registers for the bindless modelConnor Abbott2020-04-092-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Vulkan, descriptors for samplers, SSBO's, etc. are collected into descriptor sets, and shaders can use multiple descriptor sets. At command-recording time, users can swap out only some of the descriptor sets, and the driver is supposed to do the minimum amount necessary to update any internal binding tables, knowing that only some of the descriptors have changed. With the old binding model, focused on GL, where there are separate tables for each type of resource, we can do somewhat better than now by preserving descriptors from lower descriptor sets when switching higher descriptor sets. However we still have to copy around descriptors before each draw. At least for a6xx, qualcomm went further, essentially copying the Vulkan binding model as an alternate way to load resources. There's an array of registers (actually an array for compute and one for everything else), where each register holds a pointer to a descriptor set that can contain various different descriptor types. The descriptors are padded out to 16 dwords, so that every instruction can use an index instead of a dword offset. It's called "bindless", I think, because it can also be used to implement the old GL bindless extensions (presumably it allows more samplers and textures than the old model). This commit adds the register and cmdstream parts. Next up will be the instruction encoding. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* freedreno/a6xx: Add UBO size fieldConnor Abbott2020-04-091-1/+1
| | | | | | | Verified with the vulkan blob, which uses ldc and UBO descriptors, and turnip will too soon. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* tu: ir3: Emit push constants directlyConnor Abbott2020-04-096-26/+86
| | | | | | | | | | | Carve out some space at the beginning for push constants, and push them directly, rather than remapping them to a UBO and then relying on the UBO pushing code. Remapping to a UBO is easy now, where there's a single table of UBO's, but with the bindless model it'll be a lot harder. I haven't removed all the code to move the remaining UBO's over by 1, though, because it's going to all get rewritten with bindless anyways. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* tu: Dump out shader assembly when requestedConnor Abbott2020-04-091-0/+14
| | | | | | We don't use the ir3 variant machinery, so we have to do this ourselves. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* turnip: new clear/blit implementation with shader path fallbackJonathan Marek2020-04-0915-1990/+2578
| | | | | | | | | The shader path is used to implement the following cases: * stencil aspect mask on D24S8 (for image_to_buffer,buffer_to_image) * clear/copy msaa destination (2D engine can't have msaa dest) Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: add vk_format_is_snorm/is_floatJonathan Marek2020-04-091-0/+12
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: rework format helpersJonathan Marek2020-04-096-29/+41
| | | | | | | | | | * Take tile_mode as input directly * tu6_format_gmem to tu6_base_format, use may not be limited to GMEM * Add new helpers that will return the correct tile_mode as for image level as part of the format. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: use dirty bits for dynamic viewport/scissor stateJonathan Marek2020-04-092-8/+16
| | | | | | | | CmdClearAttachments shader path will overwrite this state, so it needs to be re-emitted with dirty bits in that case. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: save attachment samples in renderpass stateJonathan Marek2020-04-092-4/+5
| | | | | | | | This is needed to be able to know the number of samples during CmdClearAttachments which can be used while the framebuffer is unknown. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: disable 8x msaaJonathan Marek2020-04-092-5/+6
| | | | | | | Not everything supports 8x msaa, and the blob doesn't support it at all. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: fix nir validate failure from push constant loweringJonathan Marek2020-04-091-0/+3
| | | | | | | Fixes newly added checks in nir validate failing. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: split up gmem/tile alignmentJonathan Marek2020-04-094-20/+12
| | | | | | | Note: the x1/y1 align in tu6_emit_blit_scissor was broken Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: RB_CCU_CNTL fixesJonathan Marek2020-04-094-16/+19
| | | | | | | | | * Correct bypass value for a618 * Bypass value for blitter * Don't set RB_CCU_CNTL again unnecessarily in tu6_emit_binning_pass Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* freedreno/registers: add RB_CCU_CNTL bitfieldsJonathan Marek2020-04-093-7/+23
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: use buffer size instead of bo size for VFD_FETCH_SIZEJonathan Marek2020-04-091-1/+1
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4224>
* turnip: improve vertex input handlingJonathan Marek2020-04-095-80/+62
| | | | | | | | | Emit vertexBindingDescriptionCount bindings, instead of one per attribute. Verified with dEQP-VK.pipeline.vertex_input.* Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4224>
* turnip: fix compute shaders crashing after geometry shader changeJonathan Marek2020-04-081-4/+6
| | | | | | | Fixes: 1af71bee734da7d8 ("turnip: Set has_gs in ir3_shader_key") Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4483>
* turnip: Drop dep_llvm from dependenciesKristian H. Kristensen2020-04-071-1/+0
| | | | | Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4478> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4478>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 00:06:27 +0000