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* turnip: implement VK_EXT_sampler_filter_minmaxJonathan Marek2020-04-221-1/+8
* turnip: implement VK_EXT_filter_cubicJonathan Marek2020-04-221-0/+1
* turnip: implement VK_EXT_sample_locationsJonathan Marek2020-04-221-14/+25
* freedreno/a6xx: Expand various varying-count bitfieldsConnor Abbott2020-04-211-6/+6
* freedreno/turnip: Update GRAS_LAYER_CNTL to GRAS_MAX_LAYER_INDEXBrian Ho2020-04-151-4/+2
* freedreno/a6xx: Add registers for the bindless modelConnor Abbott2020-04-092-0/+39
* freedreno/a6xx: Add UBO size fieldConnor Abbott2020-04-091-1/+1
* turnip: new clear/blit implementation with shader path fallbackJonathan Marek2020-04-091-1/+6
* freedreno/registers: add RB_CCU_CNTL bitfieldsJonathan Marek2020-04-091-1/+13
* turnip: improve vertex input handlingJonathan Marek2020-04-091-2/+4
* freedreno: Cleanup event namesConnor Abbott2020-04-021-4/+6
* freedreno/a6xx: register updateRob Clark2020-03-271-1/+3
* freedreno/registers: more GRAS_CL_CNTL bits, Z_CLAMPJonathan Marek2020-03-241-3/+17
* tu: Fix border color with compute shadersConnor Abbott2020-03-171-0/+6
* turnip: add r5g5b5a1_unorm/b5g5r5a1_unorm formatsJonathan Marek2020-02-281-0/+1
* freedreno/registers: cleanup CP_SET_MARKERRob Clark2020-02-181-3/+14
* freedreno/a6xx: few register updatesRob Clark2020-02-182-3/+66
* freedreno/registers: teach gen_header.py about a3xx_regidRob Clark2020-02-182-6/+2
* freedreno/a6xx: document some unknown bitsJonathan Marek2020-02-141-1/+9
* freedreno: name sysmem color/depth flush eventsJonathan Marek2020-02-141-2/+3
* freedreno/a6xx: use single format enumJonathan Marek2020-02-121-229/+136
* freedreno: Fix CP_COND_EXECConnor Abbott2020-02-051-1/+1
* freedreno: Add CP_REG_WRITE documentationConnor Abbott2020-02-051-0/+32
* freedreno: Fix CP_COND_REG_EXEC bit positionsConnor Abbott2020-02-051-3/+3
* freedreno: Document CP_INDIRECT_BUFFER_CHAINConnor Abbott2020-01-241-0/+6
* freedreno: Document CP_UNK_A6XX_55Connor Abbott2020-01-242-23/+62
* freedreno: Document CP_COND_REG_EXEC moreConnor Abbott2020-01-241-1/+28
* freedreno: Fix OUT_REG() on address regs without a .bo supplied.Eric Anholt2020-01-231-0/+1
* freedreno: Add some missing a6xx address declarations.Eric Anholt2020-01-231-0/+5
* freedreno/registers: document vertex/instance id offset bitsJonathan Marek2019-12-191-1/+6
* freedreno/a6xx: RB6_R8G8B8 is actually 32 bit RGBXKristian H. Kristensen2019-12-191-1/+1
* freedreno: Fix CP_MEM_TO_REG flag definitionsConnor Abbott2019-12-181-2/+4
* a6xx: Add more CP packetsConnor Abbott2019-12-181-14/+277
* freedreno/a6xx: Document the CP_SET_DRAW_STATE enable bitsKristian H. Kristensen2019-12-171-7/+3
* freedreno/registers: add a6xx texture format for stencil samplerJonathan Marek2019-12-121-0/+3
* freedreno/registers: Add 64 bit address registersKristian H. Kristensen2019-12-111-0/+13
* freedreno: New struct packing macrosKristian H. Kristensen2019-12-112-35/+171
* freedreno/registers: Remove duplicate register definitionsKristian H. Kristensen2019-12-115-16/+1
* freedreno/a6xx: fix LRZ logicRob Clark2019-12-101-2/+1
* freedreno/registers: add missing MH perfcounter enum for a2xxJonathan Marek2019-11-271-0/+185
* freedreno/regs: update UBWC related bitsJonathan Marek2019-11-211-5/+9
* freedreno/registers: fix a6xx_2d_blit_cntl ROTATEJonathan Marek2019-11-171-2/+1
* freedreno/a6xx: Program state for tessellation stagesKristian H. Kristensen2019-11-071-0/+5
* freedreno/a6x: Rename z/s formatsKristian H. Kristensen2019-11-071-2/+2
* freedreno/a6xx: Fix layered texture type enumKristian H. Kristensen2019-11-071-3/+4
* freedreno/a6xx: Clear sysmem with CP_BLITKristian H. Kristensen2019-11-071-0/+4
* freedreno/registers: Add comments about primitive countersKristian H. Kristensen2019-11-071-12/+10
* freedreno/registers: Move SP_PRIMITIVE_CNTL and SP_VS_VPC_DSTKristian H. Kristensen2019-11-071-28/+28
* freedreno/registers: Fix typoKristian H. Kristensen2019-11-071-1/+1
* freedreno/a2xx: add missing vertex formats (SSCALE/USCALE/FIXED)Jonathan Marek2019-10-301-1/+1
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