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* turnip: implement VK_EXT_sampler_filter_minmaxJonathan Marek2020-04-221-1/+8
| | | | | | | Passes dEQP-VK.pipeline.sampler.view_type.* Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4662>
* turnip: implement VK_EXT_filter_cubicJonathan Marek2020-04-221-0/+1
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4672>
* turnip: implement VK_EXT_sample_locationsJonathan Marek2020-04-221-14/+25
| | | | | | | | | | | | | Passes tests in: dEQP-VK.pipeline.multisample.sample_locations_ext.* Note that these tests fail because of gl_PrimitiveID not working correctly: dEQP-VK.pipeline.multisample.sample_locations_ext.verify_location.* Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4665>
* freedreno/a6xx: Expand various varying-count bitfieldsConnor Abbott2020-04-211-6/+6
| | | | | | | | | The extra bit needs to be used when using the maximum of 128 varying components. I confirmed that PC_PRIMITIVE_CNTL_1 and SP_PRIMITIVE_CNTL are expanded using a trace of the Vulkan blob with the maximum number of varyings, and changed the others by analogy. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4641>
* freedreno/turnip: Update GRAS_LAYER_CNTL to GRAS_MAX_LAYER_INDEXBrian Ho2020-04-151-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | After some experimentation, I believe that GRAS_LAYER_CNTL is actually just a count register storing the number of layers in the render target. While debugging cube_array geometry tests, I noticed that the blob was setting an unknown 0x8 to LAYER_CNTL, so I checked the value of LAYER_CNTL for various layer sizes: 1: LAYER_CNTL=0 2: LAYER_CNTL=1 3: LAYER_CNTL=2 4: LAYER_CNTL=3 9: LAYER_CNTL=8 256: LAYER_CNTL=255 2000: LAYER_CNTL=1999 Seems like this register just stores a count of the largest layer that can be written to via gl_Layer. This commit updates the reg docs, freedreno's gs implementation, and turnip's gs implementation. Fixes dEQP-VK.geometry.layered.cube_array.* Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4541>
* freedreno/a6xx: Add registers for the bindless modelConnor Abbott2020-04-092-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Vulkan, descriptors for samplers, SSBO's, etc. are collected into descriptor sets, and shaders can use multiple descriptor sets. At command-recording time, users can swap out only some of the descriptor sets, and the driver is supposed to do the minimum amount necessary to update any internal binding tables, knowing that only some of the descriptors have changed. With the old binding model, focused on GL, where there are separate tables for each type of resource, we can do somewhat better than now by preserving descriptors from lower descriptor sets when switching higher descriptor sets. However we still have to copy around descriptors before each draw. At least for a6xx, qualcomm went further, essentially copying the Vulkan binding model as an alternate way to load resources. There's an array of registers (actually an array for compute and one for everything else), where each register holds a pointer to a descriptor set that can contain various different descriptor types. The descriptors are padded out to 16 dwords, so that every instruction can use an index instead of a dword offset. It's called "bindless", I think, because it can also be used to implement the old GL bindless extensions (presumably it allows more samplers and textures than the old model). This commit adds the register and cmdstream parts. Next up will be the instruction encoding. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* freedreno/a6xx: Add UBO size fieldConnor Abbott2020-04-091-1/+1
| | | | | | | Verified with the vulkan blob, which uses ldc and UBO descriptors, and turnip will too soon. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* turnip: new clear/blit implementation with shader path fallbackJonathan Marek2020-04-091-1/+6
| | | | | | | | | The shader path is used to implement the following cases: * stencil aspect mask on D24S8 (for image_to_buffer,buffer_to_image) * clear/copy msaa destination (2D engine can't have msaa dest) Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* freedreno/registers: add RB_CCU_CNTL bitfieldsJonathan Marek2020-04-091-1/+13
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>
* turnip: improve vertex input handlingJonathan Marek2020-04-091-2/+4
| | | | | | | | | Emit vertexBindingDescriptionCount bindings, instead of one per attribute. Verified with dEQP-VK.pipeline.vertex_input.* Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4224>
* freedreno: Cleanup event namesConnor Abbott2020-04-021-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that every *_TS event, i.e. every event which requires a seqno pointer, also allows generating an interrupt in the kernel, at least since a3xx. And furthermore these interrupts are named by the kgsl kernel driver and already in envytools. Therefore it's possible to map out what the *_TS events are with 100% certainty, given access to the hardware, by sending a CP_EVENT_WRITE with bit 31 set, unmasking all interrupts in the kernel, and logging which ones get hit. I've done this for a6xx, and I've also looked at the a5xx firmware, and the list of TS interrupts is the same as a6xx, so I have a pretty good idea of what the a5xx events are. I also fixed a few related things along the way: - VIZQUERY_END overlaps with WT_DONE_TS, but VIZQUERY_START was also a mess, with neither VIZQUERY_START nor HLSQ_FLUSH using variants. I added what seems like reasonable variants, based on the existing comment and the fact that HLSQ_FLUSH is only used in Mesa with a3xx and a4xx. - CACHE_FLUSH_AND_INVALIDATE seems to come straight from R600, and I have no idea if it's actually valid with a2xx, but given that RB_DONE_TS exists in the interrupt mask since a3xx, I guessed that RB_DONE_TS hasn't changed position since then and put it down as a3xx+ and limited CACHE_FLUSH_AND_INVALIDATE to a2xx. Someone with the relevant hardware should be able to confirm. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4065>
* freedreno/a6xx: register updateRob Clark2020-03-271-1/+3
| | | | | | | | No functional change, and this register isn't used in userspace. Just syncing from envytools tree to eliminate the delta. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/registers: more GRAS_CL_CNTL bits, Z_CLAMPJonathan Marek2020-03-241-3/+17
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4293>
* tu: Fix border color with compute shadersConnor Abbott2020-03-171-0/+6
| | | | | | | | | | | | | | I wasn't able to find any CTS tests that used compute shaders with samplers and set a border color, so I hacked one of the tests included with amber: https://gist.github.com/cwabbott0/e72f0ed8259b84ed6bf3920c68fefee6 The register was found via looking at dumps of the Vulkan blob, and setting it fixes this test. Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4204> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4204>
* turnip: add r5g5b5a1_unorm/b5g5r5a1_unorm formatsJonathan Marek2020-02-281-0/+1
| | | | | | | | | | r5g5b5a1/b5g5r5a1 tiled/ubwc is the same as a1r5g5b5 (in memory), but linear is read as 1_5_5_5 and written with 5_5_5_1 with swap. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
* freedreno/registers: cleanup CP_SET_MARKERRob Clark2020-02-181-3/+14
| | | | | | | | | | | 1) Name RM6_COMPUTE, and rename RM6_ENDVIS (from RM6_BLIT) to better reflect what it actually does 2) Cleanup open-coded mode enum values 3) Removed unused 0x10 Signed-off-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>
* freedreno/a6xx: few register updatesRob Clark2020-02-182-3/+66
| | | | | | | | | Nothing used by mesa, but crashdec tool uses a few of these. And since the practice is these days to sync mesa->envytools, adding these on the mesa side first. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>
* freedreno/registers: teach gen_header.py about a3xx_regidRob Clark2020-02-182-6/+2
| | | | | | | | | | This is a builtin type (treated as uint, but with special type-aware decoding) in envytools/cffdump. Lets teach gen_header.py about it and drop the enum hack in the xml so I don't have to keep deleting the enum when I sync the xml back to the freedreno envytools tree. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3833>
* freedreno/a6xx: document some unknown bitsJonathan Marek2020-02-141-1/+9
| | | | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
* freedreno: name sysmem color/depth flush eventsJonathan Marek2020-02-141-2/+3
| | | | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
* freedreno/a6xx: use single format enumJonathan Marek2020-02-121-229/+136
| | | | | | | | | | | | | | | Loses some information about which formats can be used in which cases, but we encode that information in the format table anyway. Important notes: * RB6_R10G10B10A2_UNORM becomes FMT6_R10G10B10A2_UNORM_DEST * TFMT6_8_8_8_UNORM becomes FMT6_8_8_8_X8_UNORM (not FMT6_8_8_8_UNORM) Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3798> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3798>
* freedreno: Fix CP_COND_EXECConnor Abbott2020-02-051-1/+1
| | | | | | | | | Noticed while looking at a trace of the Vulkan blob. Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
* freedreno: Add CP_REG_WRITE documentationConnor Abbott2020-02-051-0/+32
| | | | | | | | | Document the first DWORD, which at least for the Vulkan blob on a640 isn't always 2. Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
* freedreno: Fix CP_COND_REG_EXEC bit positionsConnor Abbott2020-02-051-3/+3
| | | | | | Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
* freedreno: Document CP_INDIRECT_BUFFER_CHAINConnor Abbott2020-01-241-0/+6
| | | | | | | | | This will let us use batch chaining instead of growing batches on a5xx and a6xx. Reviewed-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
* freedreno: Document CP_UNK_A6XX_55Connor Abbott2020-01-242-23/+62
| | | | | Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3537>
* freedreno: Document CP_COND_REG_EXEC moreConnor Abbott2020-01-241-1/+28
| | | | | | | | | The vulkan blob uses the RENDER_MODE mode to condition a blit on the render mode in traces of a dEQP triangle test. Reviewed-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182>
* freedreno: Fix OUT_REG() on address regs without a .bo supplied.Eric Anholt2020-01-231-0/+1
| | | | | | | | | Sometimes you want to zero out an address by supplying a NULL BO, but without this we would end up only emitting one dword. Increases size of fd6_gmem.o by .8%, though it's not clear to me why (no obvious terrible codegen happening) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
* freedreno: Add some missing a6xx address declarations.Eric Anholt2020-01-231-0/+5
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
* freedreno/registers: document vertex/instance id offset bitsJonathan Marek2019-12-191-1/+6
| | | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3162>
* freedreno/a6xx: RB6_R8G8B8 is actually 32 bit RGBXKristian H. Kristensen2019-12-191-1/+1
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kristian H. Kristensen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>
* freedreno: Fix CP_MEM_TO_REG flag definitionsConnor Abbott2019-12-181-2/+4
| | | | | | | | | | | These actually mean something completely different, at least on A5xx and A6xx. The only other usage of the old flags on something older than A6xx was a typo, so I don't know if it was always this way, but at the same time it means that we don't have to worry too much about that. Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
* a6xx: Add more CP packetsConnor Abbott2019-12-181-14/+277
| | | | | | | | | | | | | | | | | | | | And add fields uncovered by looking at the firmware. I think this covers all the memory, register, and scratch manipulation opcodes that exist on A6xx, plus one additional nice find for Vulkan and describing a previously unknown opcode and documenting CP_WAIT_REG_MEM. Note that the bits for the CP_REG_TO_MEM count, as well as the formula for computing the actual count for both CP_REG_TO_MEM and CP_MEM_TO_REG, are changed because the A630 SQE firmware actually does something different. I haven't investigated older microcodes to see whether this extends back to A5xx and A4xx, but the only non-A6xx uses of this field result in the same bit-pattern when using the A6xx bit range and formula, so it should be safe to change the definition universally. Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
* freedreno/a6xx: Document the CP_SET_DRAW_STATE enable bitsKristian H. Kristensen2019-12-171-7/+3
| | | | | | | | | | There are bits for binning, gmem and sysmem. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]> Signed-off-by: Kristian H. Kristensen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3131> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3131>
* freedreno/registers: add a6xx texture format for stencil samplerJonathan Marek2019-12-121-0/+3
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/registers: Add 64 bit address registersKristian H. Kristensen2019-12-111-0/+13
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]> Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno: New struct packing macrosKristian H. Kristensen2019-12-112-35/+171
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]> Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/registers: Remove duplicate register definitionsKristian H. Kristensen2019-12-115-16/+1
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]> Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: fix LRZ logicRob Clark2019-12-101-2/+1
| | | | | | | | | | | | In particular, we need to invalidate the LRZ state when we cannot be confident in what the Z state would be during rendering: 1) depth test modes not supported by LRZ 2) stencil test, which would require full rasterization and stencil test in the binning pass (whereas LRZ normally just needs to determine the min and max z value in an 8x8 quad) Signed-off-by: Rob Clark <[email protected]>
* freedreno/registers: add missing MH perfcounter enum for a2xxJonathan Marek2019-11-271-0/+185
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/regs: update UBWC related bitsJonathan Marek2019-11-211-5/+9
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/registers: fix a6xx_2d_blit_cntl ROTATEJonathan Marek2019-11-171-2/+1
| | | | | | | | | A change from b7093882 got overwritten by 610c8c93 Fixes: 610c8c93 ("freedreno/registers: Update with GS, HS and DS registers") Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6xx: Program state for tessellation stagesKristian H. Kristensen2019-11-071-0/+5
| | | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6x: Rename z/s formatsKristian H. Kristensen2019-11-071-2/+2
| | | | | | | | | | What we call eRB6_Z24_UNORM_S8_UINT now is actually RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 and RB6_X8Z24_UNORM is actually RB6_Z24_UNORM_S8_UINT. Signed-off-by: Kristian H. Kristensen <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6xx: Fix layered texture type enumKristian H. Kristensen2019-11-071-3/+4
| | | | | | | | 2D array textures and 3D textures are different enum values after all. Signed-off-by: Kristian H. Kristensen <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a6xx: Clear sysmem with CP_BLITKristian H. Kristensen2019-11-071-0/+4
| | | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/registers: Add comments about primitive countersKristian H. Kristensen2019-11-071-12/+10
| | | | | | | | Adding comments about best guess at what the counters count. Signed-off-by: Kristian H. Kristensen <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/registers: Move SP_PRIMITIVE_CNTL and SP_VS_VPC_DSTKristian H. Kristensen2019-11-071-28/+28
| | | | | | | | Move these two to be in order with the other VS regs. Signed-off-by: Kristian H. Kristensen <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/registers: Fix typoKristian H. Kristensen2019-11-071-1/+1
| | | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a2xx: add missing vertex formats (SSCALE/USCALE/FIXED)Jonathan Marek2019-10-301-1/+1
| | | | | | | | Mostly for vertex formats, but they are supported as texture formats too (untested however). Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 08:40:48 +0000