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path: root/src/freedreno/ir3
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* ir3: Disable copy prop for immediate ldlw offsetsBrian Ho2020-04-031-0/+3
* freedreno/turnip: Use the NIR info to decide if we need helper invocations.Eric Anholt2020-03-313-1/+7
* freedreno/ir3: fix android buildRob Clark2020-03-311-2/+2
* meson: inline `inc_common`Eric Engestrom2020-03-281-1/+1
* freedreno/ir3/ra: re-work a6xx merged register file conflictsRob Clark2020-03-271-18/+10
* freedreno/ir3/ra: split building regs/classes and conflictsRob Clark2020-03-272-22/+73
* freedreno/ir3/ra: pick higher numbered scalars in first passRob Clark2020-03-274-17/+113
* freedreno/ir3/ra: compute register target from liverangesRob Clark2020-03-272-82/+209
* freedreno/ir3/ra: fix array liverangesRob Clark2020-03-271-1/+1
* freedreno/ir3/ra: add def/use iteratorsRob Clark2020-03-272-133/+202
* freedreno/ir3/ra: drop extending output live-rangesRob Clark2020-03-271-7/+0
* freedreno/ir3/ra: add helper to map name to arrayRob Clark2020-03-271-1/+24
* freedreno/ir3/ra: fix target register calculationRob Clark2020-03-271-1/+1
* freedreno/ir3/ra: add helper to map name to instructionRob Clark2020-03-271-23/+36
* freedreno/ir3/ra: split-upRob Clark2020-03-274-352/+422
* freedreno/ir3/ra: add debug option for RA debug msgsRob Clark2020-03-273-16/+37
* freedreno/ir3: convert debug bitfield to BITFIELD_BIT()Rob Clark2020-03-271-12/+12
* freedreno/ir3: reformat disasm outputRob Clark2020-03-271-7/+17
* freedreno/ir3: fix bogus register footprint with tess/gsRob Clark2020-03-271-0/+3
* freedreno/ir3: remove unused helperRob Clark2020-03-271-10/+0
* freedreno/ir3: add bary_ij as src for meta:tex_prefetchRob Clark2020-03-271-9/+4
* freedreno/ir3: small cleanup and commentsRob Clark2020-03-2717-71/+77
* freedreno/ir3: enable nir_opt_loop_unroll on a6xxHyunjun Ko2020-03-241-1/+1
* freedreno/ir3: Lower bools to bitsizeNeil Roberts2020-03-241-1/+1
* freedreno: Switch to exposing only half-integer pixel centers.Eric Anholt2020-03-191-4/+1
* turnip: Gather information for transform feedbackHyunjun Ko2020-03-121-0/+1
* freedreno/ir3: try to avoid syncsRob Clark2020-03-101-1/+55
* freedreno/ir3: round-robin RARob Clark2020-03-101-4/+163
* freedreno/ir3: track register usage in first RA passRob Clark2020-03-101-0/+41
* freedreno/ir3: fix has_latency_to_hideRob Clark2020-03-101-1/+8
* freedreno/ir3: split out has_latency_to_hide()Rob Clark2020-03-102-25/+25
* freedreno/ir3: add simplified stall estimationRob Clark2020-03-102-1/+14
* freedreno/ir3: remove extra nops inserted in schedulerRob Clark2020-03-102-25/+0
* freedreno/ir3: also lower lowp frag outputsRob Clark2020-03-101-1/+2
* freedreno/ir3: Don't fold conversions into signKristian H. Kristensen2020-03-091-0/+1
* freedreno/ir3: add assertRob Clark2020-02-281-0/+1
* freedreno/ir3: fix assert with getinfoRob Clark2020-02-281-2/+3
* freedreno/ir3: don't precolor unassigned inputsRob Clark2020-02-281-0/+3
* freedreno/ir3: fix crash with samgq workaroundRob Clark2020-02-281-1/+2
* freedreno/ir3: update SFU delayRob Clark2020-02-284-13/+19
* freedreno/ir3: track half-precision live valuesRob Clark2020-02-283-26/+43
* freedreno/ir3: don't hide latency when there is none to hideRob Clark2020-02-281-5/+52
* freedreno/ir3: rewrite regmask to better support a6xx+Rob Clark2020-02-281-23/+53
* freedreno/ir3: remove regmask_set_if_not()Rob Clark2020-02-281-21/+0
* freedreno/ir3: remove from_tgsiRob Clark2020-02-281-3/+0
* freedreno/ir3: allow block->predecessors to be nullRob Clark2020-02-241-1/+4
* freedreno/computerator: polish out some of the rustRob Clark2020-02-241-0/+3
* freedreno: Switch to using lowered image intrinsics.Eric Anholt2020-02-246-137/+92
* freedreno/ir3: Fix the arg to ir3_get_num_components_for_image_format()Eric Anholt2020-02-242-2/+2
* freedreno/ir3: Reuse glsl_get_sampler_dim_coordinate_components() in tex_info.Eric Anholt2020-02-241-21/+3