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* freedreno: Switch to exposing only half-integer pixel centers.Eric Anholt2020-03-191-4/+1
* turnip: Gather information for transform feedbackHyunjun Ko2020-03-121-0/+1
* freedreno/ir3: try to avoid syncsRob Clark2020-03-101-1/+55
* freedreno/ir3: round-robin RARob Clark2020-03-101-4/+163
* freedreno/ir3: track register usage in first RA passRob Clark2020-03-101-0/+41
* freedreno/ir3: fix has_latency_to_hideRob Clark2020-03-101-1/+8
* freedreno/ir3: split out has_latency_to_hide()Rob Clark2020-03-102-25/+25
* freedreno/ir3: add simplified stall estimationRob Clark2020-03-102-1/+14
* freedreno/ir3: remove extra nops inserted in schedulerRob Clark2020-03-102-25/+0
* freedreno/ir3: also lower lowp frag outputsRob Clark2020-03-101-1/+2
* freedreno/ir3: Don't fold conversions into signKristian H. Kristensen2020-03-091-0/+1
* freedreno/ir3: add assertRob Clark2020-02-281-0/+1
* freedreno/ir3: fix assert with getinfoRob Clark2020-02-281-2/+3
* freedreno/ir3: don't precolor unassigned inputsRob Clark2020-02-281-0/+3
* freedreno/ir3: fix crash with samgq workaroundRob Clark2020-02-281-1/+2
* freedreno/ir3: update SFU delayRob Clark2020-02-284-13/+19
* freedreno/ir3: track half-precision live valuesRob Clark2020-02-283-26/+43
* freedreno/ir3: don't hide latency when there is none to hideRob Clark2020-02-281-5/+52
* freedreno/ir3: rewrite regmask to better support a6xx+Rob Clark2020-02-281-23/+53
* freedreno/ir3: remove regmask_set_if_not()Rob Clark2020-02-281-21/+0
* freedreno/ir3: remove from_tgsiRob Clark2020-02-281-3/+0
* freedreno/ir3: allow block->predecessors to be nullRob Clark2020-02-241-1/+4
* freedreno/computerator: polish out some of the rustRob Clark2020-02-241-0/+3
* freedreno: Switch to using lowered image intrinsics.Eric Anholt2020-02-246-137/+92
* freedreno/ir3: Fix the arg to ir3_get_num_components_for_image_format()Eric Anholt2020-02-242-2/+2
* freedreno/ir3: Reuse glsl_get_sampler_dim_coordinate_components() in tex_info.Eric Anholt2020-02-241-21/+3
* freedreno/ir3: Lower output precisionKristian H. Kristensen2020-02-243-0/+54
* freedreno/ir3: handle half registers for arrays during register allocation.Hyunjun Ko2020-02-243-9/+38
* freedreno/ir3: Add new ir3 pass to fold out fp16 conversionsHyunjun Ko2020-02-244-0/+131
* freedreno/ir3: Fold const only when the type is floatHyunjun Ko2020-02-071-0/+11
* freedreno/ir3: put the conversion back for half const to the right place.Hyunjun Ko2020-02-071-6/+6
* freedreno/ir3: Add cat4 mediump opcodesHyunjun Ko2020-02-072-0/+18
* freedreno/ir3: fold const conversion into consumerRob Clark2020-02-072-1/+20
* freedreno/ir3: fix printing half constant registers.Hyunjun Ko2020-02-071-3/+4
* freedreno/ir3: Set IR3_REG_HALF flag on src as well in immediate MOVKristian H. Kristensen2020-02-071-1/+1
* glsl,nir: Switch the enum representing shader image formats to PIPE_FORMAT.Eric Anholt2020-02-054-66/+7
* freedreno/ir3: fix a dirty lieRob Clark2020-02-011-7/+4
* freedreno/ir3: simplify split from collectRob Clark2020-02-011-0/+10
* freedreno/ir3: create fragcoord instructions in input blockRob Clark2020-02-011-2/+2
* freedreno/ir3: remove unused tex arg harderRob Clark2020-02-013-19/+12
* freedreno/ir3: add RA sanity checkRob Clark2020-02-011-0/+33
* freedreno/ir3: two pass register allocationRob Clark2020-02-012-60/+297
* freedreno/ir3: don't precolor unused inputsRob Clark2020-02-011-1/+2
* freedreno/ir3: add is_tex_or_prefetch()Rob Clark2020-02-013-2/+7
* freedreno/ir3: number instructions from oneRob Clark2020-02-011-1/+1
* freedreno/ir3: post-RA sched passRob Clark2020-02-015-5/+678
* freedreno/ir3: fix kill schedulingRob Clark2020-02-012-1/+2
* freedreno/ir3/ra: make use()/def() functions instead of macrosRob Clark2020-02-011-15/+24
* freedreno/ir3: a bit more optmsgs debugRob Clark2020-02-011-0/+10
* freedreno/ir3: move atomic fixup after RARob Clark2020-02-013-28/+38
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