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* freedreno/ir3/print: print (r) flagRob Clark2020-06-161-0/+3
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3/print: print cat2 conditionRob Clark2020-05-191-0/+22
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5048>
* freedreno/ir3: make input/output iterators declare cursor ptrRob Clark2020-05-191-2/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5048>
* freedreno/ir3: Sync some new changes from envytools.Eric Anholt2020-05-041-2/+2
| | | | | | | | With this I also brought in a few new control flow instruction disasm tests that I'd made back when I wrote the disasm test, but which were too far from correct to include until now. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
* ir3: Fix LDC offset unitsConnor Abbott2020-04-151-0/+2
| | | | | | | | | | | | I had missed that LDC actually uses vec4 units for its offset. This means that we have to create a new instruction, and lower it in ir3_nir_lower_io_offsets, similar to the existing SSBO instructions. Unfortunately we can't assume that loads are always vec4-aligned, so we have to use the alignment information that NIR gives us. Unfortunately, it's currently woefully inadequate, and will have to be fixed to give us good codegen in the future. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4568>
* freedreno/ir3: rename depth->dceRob Clark2020-04-131-1/+0
| | | | | | | | Since DCE is the only remaining function of this pass, after the pre-RA scheduler rewrite. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: better cleanup when removing unused instructionsRob Clark2020-04-131-1/+5
| | | | | | | | | | | | Do a better job of pruning when removing unused instructions, including cleaning up dangling false-deps. This introduces a new ssa src pointer iterator, which makes it easy to clear links without having to think about whether it is a normal ssa src or a false-dep. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* ir3: Plumb through bindless supportConnor Abbott2020-04-091-2/+18
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* freedreno/ir3: small cleanup and commentsRob Clark2020-03-271-1/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3: allow block->predecessors to be nullRob Clark2020-02-241-1/+4
| | | | | | | | | This way we can also use ir3_print from computerator, which mostly bypasses the ir3_block construct (since it doesn't need to do scheduling, etc) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
* freedreno/ir3: remove unused tex arg harderRob Clark2020-02-011-4/+0
| | | | | | | | Just killing the SSA link isn't enough. It confuses RA, legalize, and postsched to see a bogus unused reg. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
* freedreno/ir3: add iterator macrosRob Clark2019-12-131-2/+2
| | | | | | So many open coded list iterators were getting annoying. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add scheduler tracesRob Clark2019-12-131-0/+1
| | | | | | | Add some infrastructure to trace scheduler decisions. The next patch will add some more traces, just splitting this out to reduce clutter. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add input/output iteratorsRob Clark2019-11-121-4/+3
| | | | | | | | We can at least get rid of the if-not-NULL check in a bunch of places. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: rename fanin/fanout to collect/splitRob Clark2019-11-121-4/+4
| | | | | | | | | | | If I'm going to refactor a bit to use these meta instructions to also handle input/output, then might as well cleanup the names first. Nouveau also uses collect/split for names of these meta instructions, and I like those names better. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: ir3_print tweaksRob Clark2019-11-091-46/+101
| | | | | | Handle HALF/HIGH flags in all cases, and colorize SSA src notation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: make high regs easier to see in IR dumpsRob Clark2019-10-241-0/+2
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: add meta instruction for pre-fs texture fetchRob Clark2019-10-181-0/+4
| | | | | | | | | | | | | | | | | Add a placeholder instruction to track texture fetches made prior to FS shader dispatch. These, like meta:input instructions are scheduled before any real instructions, so that RA realizes their result values are live before the first real instruction. And to give legalize a way to track usage of fetched sample requiring (sy) sync flags. There is some related special handling for varying texcoord inputs used for pre-fs-fetch, so that they are not DCE'd and remain in linkage between FS and previous stage. Note that we could almost avoid this special handling by giving meta:tex_prefetch real src arguments, except that in the FS stage, inputs are actual bary.f/ldlv instructions. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: convert block->predecessors to setRob Clark2019-08-281-4/+6
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: add Sethi–Ullman numbering passRob Clark2019-03-031-1/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: HIGH reg w/a for a6xxRob Clark2019-02-161-0/+2
| | | | | | | | | | | | | It seems like some instructions (noticed this w/ cat3), cannot read HIGH regs.. cat1 (mov/cov) can, and possibly some/all of cat2. The blob seems to stick w/ an extra mov into low regs. So lets do the same. This fixes WGID on a6xx, which unsurprisingly is related to a lot of deqp compute fails. Signed-off-by: Rob Clark <[email protected]>
* freedreno: move ir3 to common locationRob Clark2018-11-271-0/+264
Move (most of) the ir3 compiler to src/freedreno/ir3 so that it can be re-used by some future vulkan driver. The parts that are gallium specific have been refactored out and remain in the gallium driver. Getting the move done now so that it can happen before further refactoring to support a6xx specific instructions. NOTE also removes ir3_cmdline compiler tool from autotools build since that was easier than fixing it and I normally use meson build. Waiting patiently for the day that we can remove *everything* from the autotools build. Signed-off-by: Rob Clark <[email protected]>
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