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* freedreno/ir3: rename depth->dceRob Clark2020-04-131-226/+0
| | | | | | | | Since DCE is the only remaining function of this pass, after the pre-RA scheduler rewrite. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: better cleanup when removing unused instructionsRob Clark2020-04-131-1/+14
| | | | | | | | | | | | Do a better job of pruning when removing unused instructions, including cleaning up dangling false-deps. This introduces a new ssa src pointer iterator, which makes it easy to clear links without having to think about whether it is a normal ssa src or a false-dep. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* freedreno/ir3: new pre-RA schedulerRob Clark2020-04-131-19/+0
| | | | | | | | | | | | This replaces the depth-first search scheduler with a more traditional ready-list scheduler. It primarily tries to reduce register pressure (number of live values), with the exception of trying to schedule kills as early as possible. (Earlier iterations of this scheduler had a tendency to push kills later, and in particular moving texture fetches which may not be necessary ahead of kills.) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
* ir3: Plumb through support for a1.xConnor Abbott2020-04-091-3/+9
| | | | | | | | This will need to be used in some cases for the upcoming bindless support, plus ldc.k instructions which push data from a UBO to const registers. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
* freedreno/ir3/ra: pick higher numbered scalars in first passRob Clark2020-03-271-1/+17
| | | | | | | | | | | | | | | Since we are re-assigning the scalars anyways in the second pass, assign them to the highest free reg in the first pass (rather than lowest) to allow packing vecN regs as low as possible. Note this required some changes specifically for tex instructions with a single component writemask that is not necessarily .x, as previously these would get assigned in the first RA pass, and since they are still scalar, we'd end up w/ some r47.* and other similarly way-to-high assignments after the 2nd pass. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3: small cleanup and commentsRob Clark2020-03-271-3/+3
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3: update SFU delayRob Clark2020-02-281-1/+1
| | | | | | | | | | 1) emperically, 10 seems like a more accurate # than 4 2) push "soft" delay handling into ir3_delayslots(), as we should also be using it to calculate the costs that the schedulers use Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
* freedreno/ir3: add is_tex_or_prefetch()Rob Clark2020-02-011-1/+1
| | | | | | | | | | | | Some of the aspects of tex prefetch are in common with normal tex instructions, such as having a wrmask to control which components are written. Add a helper for this. This should result in actually using the prefetch wrmask to avoid fetching unneeded components. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
* freedreno/ir3: split out delay helpersRob Clark2020-02-011-66/+0
| | | | | | | | We're going to want these also for a post-RA sched pass. And also to split nop stuffing out into it's own pass. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
* compiler: add PERSP to the existing barycentric system valuesSamuel Pitoiset2020-01-291-1/+1
| | | | | | | | We need the LINEAR versions for AMD_shader_explicit_vertex_parameter. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
* freedreno/ir3: add iterator macrosRob Clark2019-12-131-6/+6
| | | | | | So many open coded list iterators were getting annoying. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: only tex instructions have wrmaskRob Clark2019-11-121-6/+3
| | | | | | | | | | | At the ir3 level, we would assume that we could use wrmask to mask off other components of an instruction returning a vecN when they are not used. Which would let RA use components not written for other live values. But this is only true for tex instructions. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: add input/output iteratorsRob Clark2019-11-121-8/+7
| | | | | | | | We can at least get rid of the if-not-NULL check in a bunch of places. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: rename fanin/fanout to collect/splitRob Clark2019-11-121-2/+2
| | | | | | | | | | | If I'm going to refactor a bit to use these meta instructions to also handle input/output, then might as well cleanup the names first. Nouveau also uses collect/split for names of these meta instructions, and I like those names better. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno/ir3: don't DCE ij_pix if used for pre-fs-texture-fetchRob Clark2019-10-181-3/+11
| | | | | | | | | | When we enable pre-dispatch texture fetch, we could have a scenario where the barycentric i/j coord sysval is not used in the shader, but only used for the varying fetch for the pre-dispatch texture fetch. In this case we need to take care not to DCE this sysval. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Add support for CHSH and CHMASK instructionsKristian H. Kristensen2019-10-171-1/+1
| | | | | | | Just add the constructors for now and special case similar to END so we don't remove them. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: track register pressure in schedRob Clark2019-03-031-1/+1
| | | | | | | | | | | | | | | Not a perfect solution, and the "pressure" target is hard-coded. But it doesn't really seem to much in the common case, and avoids exploding register usage in dEQP ssbo tests. So this should serve as a stop-gap solution until I have time to re- write the scheduler. Hurts slightly in instruction count, but gains (reduces) slightly the register usage in shader-db. Fixes ~150 dEQP-GLES31.functional.ssbo.* that were failing due to RA fail. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't remove unused input componentsRob Clark2018-12-131-1/+7
| | | | | Fixes: 0d240c22141 freedreno/ir3: don't fetch unused tex components Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix crashRob Clark2018-12-131-14/+8
| | | | | | | Fixes a crash in dEQP-GLES3.functional.shaders.fragdepth.compare.fragcoord_z Fixes: 0d240c22141 freedreno/ir3: don't fetch unused tex components Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't fetch unused tex componentsRob Clark2018-12-071-0/+27
| | | | | | | Detect when a component of an (for example) texture fetch is unused and propagate the updated wrmask back to the parent instruction. Signed-off-by: Rob Clark <[email protected]>
* freedreno: move ir3 to common locationRob Clark2018-11-271-0/+245
Move (most of) the ir3 compiler to src/freedreno/ir3 so that it can be re-used by some future vulkan driver. The parts that are gallium specific have been refactored out and remain in the gallium driver. Getting the move done now so that it can happen before further refactoring to support a6xx specific instructions. NOTE also removes ir3_cmdline compiler tool from autotools build since that was easier than fixing it and I normally use meson build. Waiting patiently for the day that we can remove *everything* from the autotools build. Signed-off-by: Rob Clark <[email protected]>
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