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* nir/search: Search for all combinations of commutative opsJason Ekstrand2019-04-083-29/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider the following search expression and NIR sequence: ('iadd', ('imul', a, b), b) ssa_2 = imul ssa_0, ssa_1 ssa_3 = iadd ssa_2, ssa_0 The current algorithm is greedy and, the moment the imul finds a match, it commits those variable names and returns success. In the above example, it maps a -> ssa_0 and b -> ssa_1. When we then try to match the iadd, it sees that ssa_0 is not b and fails to match. The iadd match will attempt to flip itself and try again (which won't work) but it cannot ask the imul to try a flipped match. This commit instead counts the number of commutative ops in each expression and assigns an index to each. It then does a loop and loops over the full combinatorial matrix of commutative operations. In order to keep things sane, we limit it to at most 4 commutative operations (16 combinations). There is only one optimization in opt_algebraic that goes over this limit and it's the bitfieldReverse detection for some UE4 demo. Shader-db results on Kaby Lake: total instructions in shared programs: 15310125 -> 15302469 (-0.05%) instructions in affected programs: 1797123 -> 1789467 (-0.43%) helped: 6751 HURT: 2264 total cycles in shared programs: 357346617 -> 357202526 (-0.04%) cycles in affected programs: 15931005 -> 15786914 (-0.90%) helped: 6024 HURT: 3436 total loops in shared programs: 4360 -> 4360 (0.00%) loops in affected programs: 0 -> 0 helped: 0 HURT: 0 total spills in shared programs: 23675 -> 23666 (-0.04%) spills in affected programs: 235 -> 226 (-3.83%) helped: 5 HURT: 1 total fills in shared programs: 32040 -> 32032 (-0.02%) fills in affected programs: 190 -> 182 (-4.21%) helped: 6 HURT: 2 LOST: 18 GAINED: 5 Reviewed-by: Thomas Helland <[email protected]>
* nir/algebraic: Add some logical OR and AND patternsJason Ekstrand2019-04-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new OR pattern has been seen in the wild and can end up being generated by GLSLang. Not sure about the other two new patterns but we may as well throw them in for completeness. While we're here, we can drop the '@bool' specifier from the one pattern because specifying True already implies 1-bit which basically implies boolean. Shader-db results on Kaby Lake: total instructions in shared programs: 15321227 -> 15321129 (<.01%) instructions in affected programs: 3594 -> 3496 (-2.73%) helped: 6 HURT: 0 total cycles in shared programs: 357481321 -> 357479725 (<.01%) cycles in affected programs: 44109 -> 42513 (-3.62%) helped: 6 HURT: 0 VkPipeline-DB results on Kaby Lake: total instructions in shared programs: 3770504 -> 3769734 (-0.02%) instructions in affected programs: 19058 -> 18288 (-4.04%) helped: 163 HURT: 0 total cycles in shared programs: 1417583701 -> 1417569727 (<.01%) cycles in affected programs: 750958 -> 736984 (-1.86%) helped: 158 HURT: 1 Reviewed-by: Timothy Arceri <[email protected]>
* nir/algebraic: Drop some @bool specifiersJason Ekstrand2019-04-051-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have one-bit booleans, we don't need to rely on looking at parent instructions in order to figure out if a value is a Boolean most of the time. We can drop these specifiers and now the optimizations will apply more generally. Shader-DB results on Kaby Lake: total instructions in shared programs: 15321168 -> 15321227 (<.01%) instructions in affected programs: 8836 -> 8895 (0.67%) helped: 1 HURT: 31 total cycles in shared programs: 357481781 -> 357481321 (<.01%) cycles in affected programs: 146524 -> 146064 (-0.31%) helped: 22 HURT: 10 total spills in shared programs: 23675 -> 23673 (<.01%) spills in affected programs: 11 -> 9 (-18.18%) helped: 1 HURT: 0 total fills in shared programs: 32040 -> 32036 (-0.01%) fills in affected programs: 27 -> 23 (-14.81%) helped: 1 HURT: 0 No change in VkPipeline-DB Looking at the instructions hurt, a bunch of them seem to be a case where doing exactly the right thing in NIR ends up doing the wrong-ish thing in the back-end because flags are dumb. In particular, there's a case where we have a MUL followed by a CMP followed by a SEL and when we turn that SEL into an OR, it uses the GRF result of the CMP rather than the flag result so the CMP can't be merged with the MUL. Those shaders appear to schedule better according to the cycle estimates so I guess it's a win? Also it helps spilling in one Car Chase compute shader. Reviewed-by: Timothy Arceri <[email protected]>
* nir: Take if_uses into account when repairing SSACaio Marcelo de Oliveira Filho2019-04-051-0/+18
| | | | | | | | | | | | | | | If a def is used as an condition before its definition, we should also consider this a case to repair. When repairing, make sure we rewrite any if conditions too. Found in while inspecting a SPIR-V conversion from a 'continue block' that contains a conditional branch. We pull the continue block up to the beggining of the loop, and the condition in the branch ends up defined afterwards. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Fixes: 364212f1ede4b "nir: Add a pass to repair SSA form"
* nir: do not pack varying with different typesSamuel Pitoiset2019-04-051-0/+13
| | | | | | | | | The current algorithm only supports packing 32-bit types. If a shader uses both 16-bit and 32-bit varyings, we shouldn't compact them together. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: Fix input/output structure matching across shader stagesSergii Romantsov2019-04-054-26/+56
| | | | | | | | | | | | | | | | | | Section 7.4.1 (Shader Interface Matching) of the OpenGL 4.30 spec says: "Variables or block members declared as structures are considered to match in type if and only if structure members match in name, type, qualification, and declaration order." Fixes: * layout-location-struct.shader_test v2: rebased against master and small fixes Signed-off-by: Vadym Shovkoplias <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108250
* glsl: remember which SSBOs are not read-only and pass it to galliumMarek Olšák2019-04-042-0/+13
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* nir: Add "viewport vector" system valuesAlyssa Rosenzweig2019-04-041-0/+5
| | | | | | | | | | | | While a partial set of viewport system values exist, these are scalar values, which is a poor fit for viewport transformations on vector ISAs like Midgard (where the vec3 values for scale and offset each need to be coherent in a vec4 uniform slot to take advantage of vectorized transform math). This patch adds vec3 scale/offset fields corresponding to the 3D Gallium viewport / glViewport+depth Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: use proper array sizing define for vectorsDave Airlie2019-04-031-4/+4
| | | | | | | If we increase the vector size in the future it would be good to not have to fix these up, this should change nothing at present. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* Revert "nir: propagate known constant values into the if-then branch"Timothy Arceri2019-04-031-60/+0
| | | | | | This reverts commit 4218b6422cf1ff70c7f0feeec699a35e88522ed7. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110311
* nir: propagate known constant values into the if-then branchTimothy Arceri2019-04-031-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Helps Max Waves / VGPR use in a bunch of Unigine Heaven shaders. shader-db results radeonsi (VEGA): Totals from affected shaders: SGPRS: 5505440 -> 5505872 (0.01 %) VGPRS: 3077520 -> 3077296 (-0.01 %) Spilled SGPRs: 39032 -> 39030 (-0.01 %) Spilled VGPRs: 16326 -> 16326 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 744 -> 744 (0.00 %) dwords per thread Code Size: 123755028 -> 123753316 (-0.00 %) bytes Compile Time: 2751028 -> 2560786 (-6.92 %) milliseconds LDS: 1415 -> 1415 (0.00 %) blocks Max Waves: 972192 -> 972240 (0.00 %) Wait states: 0 -> 0 (0.00 %) vkpipeline-db results RADV (VEGA): Totals from affected shaders: SGPRS: 160 -> 160 (0.00 %) VGPRS: 88 -> 88 (0.00 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 18268 -> 18152 (-0.63 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 26 -> 26 (0.00 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: fix a compiler warningTapani Pälli2019-04-011-1/+1
| | | | | | | Fixes implicit conversion from enumeration type 'SpvOp' warning. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* nir: add lower_all_io_to_elementsRob Clark2019-03-301-0/+1
| | | | | | | I need this part of lower_all_io_to_temps but without the actual lowering to temps part. Signed-off-by: Rob Clark <[email protected]>
* nir: print var name for load_interpolated_input tooRob Clark2019-03-301-0/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Acked-by: Karol Herbst <[email protected]>
* nir: Lock around validation fail shader dumpingJason Ekstrand2019-03-291-0/+10
| | | | | | | This prevents getting mixed-up results if a multi-threaded app has two validation errors in different threads. Reviewed-by: Timothy Arceri <[email protected]>
* nir/validate: validate that tex deref sources are actually derefsKarol Herbst2019-03-291-0/+11
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir/print: fix printing the image_array intrinsic indexKarol Herbst2019-03-291-2/+2
| | | | | | | Fixes: 0de003be0363 ("nir: Add handle/index-based image intrinsics") Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: use {0} initializer instead of {} to fix MSVC buildBrian Paul2019-03-281-2/+2
| | | | | | Trivial change. Fixes: c6ee46a75 ("nir: Add nir_alu_srcs_negative_equal")
* nir: Add partial redundancy elimination for comparesIan Romanick2019-03-285-0/+414
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass attempts to dectect code sequences like if (x < y) { z = y - x; ... } and replace them with sequences like t = x - y; if (t < 0) { z = -t; ... } On architectures where the subtract can generate the flags used by the if-statement, this saves an instruction. It's also possible that moving an instruction out of the if-statement will allow nir_opt_peephole_select to convert the whole thing to a bcsel. Currently only floating point compares and adds are supported. Adding support for integer will be a challenge due to integer overflow. There are a couple possible solutions, but they may not apply to all architectures. v2: Fix a typo in the commit message and a couple typos in comments. Fix possible NULL pointer deref from result of push_block(). Add missing (-A + B) case. Suggested by Caio. v3: Fix is_not_const_zero to work correctly with types other than nir_type_float32. Suggested by Ken. v4: Add some comments explaining how this works. Suggested by Ken. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add nir_alu_srcs_negative_equalIan Romanick2019-03-283-0/+192
| | | | | | | v2: Move bug fix in get_neg_instr from the next patch to this patch (where it was intended to be in the first place). Noticed by Caio. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add nir_const_value_negative_equalIan Romanick2019-03-284-0/+398
| | | | | | | v2: Rebase on 1-bit Boolean changes. Reviewed-by: Thomas Helland <[email protected]> [v1] Reviewed-by: Kenneth Graunke <[email protected]>
* nir/algebraic: Add missing 16-bit extract_[iu]8 patternsIan Romanick2019-03-281-0/+3
| | | | | | | | | | | | | | No shader-db changes on any Intel platform. v2: Use a loop to generate patterns. Suggested by Jason. v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would replace an extract_i8 with and extract_u8. This broke ~180 tests. This bug was introduced in v2. Reviewed-by: Matt Turner <[email protected]> [v1] Reviewed-by: Dylan Baker <[email protected]> [v2] Acked-by: Jason Ekstrand <[email protected]> [v2]
* nir/algebraic: Add missing 64-bit extract_[iu]8 patternsIan Romanick2019-03-281-0/+3
| | | | | | | | | | | | | | No shader-db changes on any Intel platform. v2: Use a loop to generate patterns. Suggested by Jason. v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would replace an extract_i8 with and extract_u8. This broke ~180 tests. This bug was introduced in v2. Reviewed-by: Matt Turner <[email protected]> [v1] Reviewed-by: Dylan Baker <[email protected]> [v2] Acked-by: Jason Ekstrand <[email protected]> [v2]
* nir/algebraic: Remove redundant extract_[iu]8 patternsIan Romanick2019-03-281-14/+4
| | | | | | | | No shader-db changes on any Intel platform. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* nir/algebraic: Fix up extract_[iu]8 after loop unrollingIan Romanick2019-03-281-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Skylake, Broadwell, and Haswell had similar results. (Skylake shown) total instructions in shared programs: 15256840 -> 15256837 (<.01%) instructions in affected programs: 4713 -> 4710 (-0.06%) helped: 3 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.06% max: 0.08% x̄: 0.06% x̃: 0.06% total cycles in shared programs: 372286583 -> 372286583 (0.00%) cycles in affected programs: 198516 -> 198516 (0.00%) helped: 1 HURT: 1 helped stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10 helped stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01% HURT stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10 HURT stats (rel) min: 0.01% max: 0.01% x̄: 0.01% x̃: 0.01% No changes on any other Intel platform. v2: Use a loop to generate patterns. Suggested by Jason. v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would replace an extract_i8 with and extract_u8. This broke ~180 tests. This bug was introduced in v2. Reviewed-by: Matt Turner <[email protected]> [v1] Reviewed-by: Dylan Baker <[email protected]> [v2] Acked-by: Jason Ekstrand <[email protected]> [v2]
* nir/deref: fix struct wrapper casts. (v3)Dave Airlie2019-03-291-2/+36
| | | | | | | | | | | llvm/spir-v spits out some struct a { struct b {} }, but it doesn't deref, it casts (struct a) to (struct b), reconstruct struct derefs instead of casts for these. v2: use ssa_def_rewrite uses, rework the type restrictions (Jason) v3: squish more stuff into one function, drop unused temp (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: propagate the access flag for store and load derefsSamuel Pitoiset2019-03-273-24/+32
| | | | | | | It was only propagated when UBO/SSBO access are lowered to offsets. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: <Jason Ekstrand [email protected]>
* nir: add nir_{load,store}_deref_with_access() helpersSamuel Pitoiset2019-03-271-3/+21
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: <Jason Ekstrand [email protected]>
* spirv: make use of the select control support in nirTimothy Arceri2019-03-271-0/+18
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108841
* nir: add support for user defined select controlTimothy Arceri2019-03-274-1/+21
| | | | | | | | | | | This will allow us to make use of the selection control support in spirv and the GL support provided by EXT_control_flow_attributes. Note this only supports if-statements as we dont support switches in NIR. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108841
* spirv: make use of the loop control support in nirTimothy Arceri2019-03-271-0/+20
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108841
* nir: add support for user defined loop controlTimothy Arceri2019-03-273-5/+22
| | | | | | | | This will allow us to make use of the loop control support in spirv and the GL support provided by EXT_control_flow_attributes. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108841
* spirv: Handle the NonUniformEXT decorationJason Ekstrand2019-03-252-0/+28
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* nir: Add access flags to deref and SSBO atomicsJason Ekstrand2019-03-252-28/+34
| | | | | | | We will need them for a new ACCESS_NON_UNIFORM flag that's about to be added in the next commit. Reviewed-by: Lionel Landwerlin <[email protected]>
* nir: Add texture sources and intrinsics for bindlessJason Ekstrand2019-03-254-10/+29
| | | | | | | | | On Intel, we have both bindless and bindful and we'd like to use them at the same time if we can so we need to be able to distinguish at the NIR level between the two. This also fixes nir_lower_tex to properly handle bindless in its tex_texture_size and get_texture_lod helpers. Reviewed-by: Lionel Landwerlin <[email protected]>
* nir: Add a lowering pass for non-uniform resource accessJason Ekstrand2019-03-255-0/+286
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir/lower_io: Add a bounds-checked 64-bit global address formatJason Ekstrand2019-03-252-6/+93
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* compiler/nir: add lowering for 16-bit ldexpIago Toral Quiroga2019-03-251-2/+7
| | | | | | | | | v2 (Topi): - Make bit-size handling order be 16-bit, 32-bit, 64-bit - Clamp lower exponent range at -28 instead of -30. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/nir: add lowering for 16-bit flrpIago Toral Quiroga2019-03-252-0/+2
| | | | | | | | | And enable it on Intel. v2: - Squash the change to enable it on Intel (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/nir: add lowering option for 16-bit fmodIago Toral Quiroga2019-03-252-0/+2
| | | | | | | | | And enable it on Intel. v2: - Squash the change to enable this lowering on Intel (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* nir: fix a few signed/unsigned comparison warningsBrian Paul2019-03-251-2/+2
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* nir/split_vars: fixup some more explicit_stride related issues.Dave Airlie2019-03-251-2/+1
| | | | | | | | | | | | | | | | With vkpipelinedb Samuel discovered a regression since we stopped stripping types at the spir-v level. This adds a check to the var splitting for the case where it asserts the type hasn't changed, when it has just created a bare type, and it's different than the original type which has an explicit stride. This also removes a pointless assert that also triggers. Fixes: 3b3653c4cf (nir/spirv: don't use bare types, remove assert in split vars for testing) Acked-by: Jason Ekstrand <[email protected]>
* spirv: Use interface type for block and buffer blockCaio Marcelo de Oliveira Filho2019-03-232-4/+36
| | | | | | | | Also handle GLSL_TYPE_INTERFACE the same way we do GLSL_TYPE_STRUCT in various places. Motivated by ARB_gl_spirv work, that will take advantage of the interface types when handling NIR coming from SPIR-V. Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Add an execution environment to the optionsCaio Marcelo de Oliveira Filho2019-03-231-0/+8
| | | | | | | | | | Also updates gl_spirv to pick the right one. At the moment nothing uses it, but upcoming functionality part of ARB_gl_spirv will use it, and we also later can be more assertful when handling certain features for each of the execution environments. Reviewed-by: Alejandro Piñeiro <[email protected]> Acked-by: Karol Herbst <[email protected]>
* nir: Handle array-deref-of-vector case in loop analysisCaio Marcelo de Oliveira Filho2019-03-221-3/+6
| | | | | | | SPIR-V can produce those for SSBO and UBO access. Found when testing the ARB_gl_spirv series. Reviewed-by: Timothy Arceri <[email protected]>
* spirv,nir: lower frexp_exp/frexp_sig inside a new NIR passSamuel Pitoiset2019-03-225-133/+216
| | | | | | | | | | This lowering isn't needed for RADV because AMDGCN has two instructions. It will be disabled for RADV in an upcoming series. While we are at it, factorize a little bit. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: use generic float types for frexp_exp and frexp_sigSamuel Pitoiset2019-03-221-2/+2
| | | | | | | Only the exponent needs to be 32-bit signed integer. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Fix anonymous union initialization with older GCC.Vinson Lee2019-03-221-4/+6
| | | | | | | | | | | | | | | | | | | | Fix this build error with GCC 4.4.7. CC nir/nir_opt_copy_prop_vars.lo nir/nir_opt_copy_prop_vars.c: In function ‘load_element_from_ssa_entry_value’: nir/nir_opt_copy_prop_vars.c:454: error: unknown field ‘ssa’ specified in initializer nir/nir_opt_copy_prop_vars.c:455: error: unknown field ‘def’ specified in initializer nir/nir_opt_copy_prop_vars.c:456: error: unknown field ‘component’ specified in initializer nir/nir_opt_copy_prop_vars.c:456: error: extra brace group at end of initializer nir/nir_opt_copy_prop_vars.c:456: error: (near initialization for ‘(anonymous).<anonymous>’) nir/nir_opt_copy_prop_vars.c:456: warning: excess elements in union initializer nir/nir_opt_copy_prop_vars.c:456: warning: (near initialization for ‘(anonymous).<anonymous>’) Fixes: 96c32d77763c ("nir/copy_prop_vars: handle load/store of vector elements") Signed-off-by: Vinson Lee <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109810 Reviewed-by: Andres Gomez <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* glsl: Cross validate variable's invariance by explicit invariance onlyDanylo Piliaiev2019-03-217-9/+30
| | | | | | | | | | | | | | | | | | 'invariant' qualifier is propagated on variables which are used to calculate other invariant variables, however when we are matching variable's declarations we should take into account only explicitly declared invariance because invariance propagation is an implementation specific detail. Thus new flag is added to ir_variable_data which indicates 'invariant' qualifier being explicitly set in the shader. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100316 Fixes: 89b60492 ('glsl: Add a pass to propagate the "invariant" and "precise" qualifiers') Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir: fix opt_if_loop_last_continue()Timothy Arceri2019-03-221-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than skipping code that looked like this: loop { ... if (cond) { do_work_1(); continue; } else { break; } do_work_2(); } Previously we would turn this into: loop { ... if (cond) { do_work_1(); continue; } else { do_work_2(); break; } } This was clearly wrong. This change checks for this case and makes sure we now leave it for nir_opt_dead_cf() to clean up. Reviewed-by: Ian Romanick <[email protected]>
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