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* compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()Iago Toral Quiroga2019-01-021-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | The 16-bit polynomial execution doesn't meet Khronos precision requirements. Also, the half-float denorm range starts at 2^(-14) and with asin taking input values in the range [0, 1], polynomial approximations can lead to flushing relatively easy. An alternative is to use the atan2 formula to compute asin, which is the reference taken by Khronos to determine precision requirements, but that ends up generating too many additional instructions when compared to the polynomial approximation. Specifically, for the Intel case, doing this adds +41 instructions to the program for each asin/acos call, which looks like an undesirable trade off. So for now we take the easy way out and fallback to using the 32-bit polynomial approximation, which is better (faster) than the 16-bit atan2 implementation and gives us better precision that matches Khronos requirements. v2: - Fallback to 32-bit using recursion (Jason). Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/spirv: implement 16-bit frexpIago Toral Quiroga2019-01-021-2/+46
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/spirv: implement 16-bit hyperbolic trigonometric functionsIago Toral Quiroga2019-01-021-18/+26
| | | | | | | | | | v2: - use nir_fadd_imm and nir_fmul_imm helpers (Jason) v3: - since we need to define one for fsub use it for fdiv too (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/spirv: implement 16-bit exp and logIago Toral Quiroga2019-01-021-2/+2
| | | | | | | v2 - use nir_fmul_imm helper (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/spirv: implement 16-bit atan2Iago Toral Quiroga2019-01-021-7/+11
| | | | | | | | | | | | v2: - fix huge_val for 16-bit, it was mean't to be 2^14 not 10^14. v3: - rebase on top of new bool sized opcodes - use nir_b2f helper - use nir_fmul_imm helper Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/spirv: implement 16-bit atanIago Toral Quiroga2019-01-021-12/+11
| | | | | | | | | v2: - use nir_fadd_imm and nir_fmul_imm helpers (Jason) - rebased on top of new sized boolean opcodes - use nir_b2f helper Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/spirv: implement 16-bit acosIago Toral Quiroga2019-01-021-2/+3
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/spirv: implement 16-bit asinIago Toral Quiroga2019-01-021-9/+14
| | | | | | | | | | | v2: - use nir_fmul_imm and nir_fadd_imm helpers (Jason) v3: - missed one case where we need to replace nir_imm_float with nir_imm_floatN_t (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add support for SpvCapabilityStorageImageMultisampleSamuel Pitoiset2018-12-201-1/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: Switch to using 1-bit Booleans for almost everythingJason Ekstrand2018-12-162-32/+32
| | | | | | | | | | | | | | | | This is a squash of a few distinct changes: glsl,spirv: Generate 1-bit Booleans Revert "Use 32-bit opcodes in the NIR producers and optimizations" Revert "nir/builder: Generate 32-bit bool opcodes transparently" nir/builder: Generate 1-bit Booleans in nir_build_imm_bool Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* nir: Add support for 1-bit data typesJason Ekstrand2018-12-161-0/+9
| | | | | | | | | | | | | | This commit adds support for 1-bit Booleans and integers. Booleans obviously take a value of true or false. Because we have to define the semantics of 1-bit signed and unsigned integers, we define uint1_t to take values of 0 and 1 and int1_t to take values of 0 and -1. 1-bit arithmetic is then well-defined in the usual way, just with fewer bits. The definition of int1_t and uint1_t doesn't usually matter but we do need something for purposes of constant folding. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-161-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a squash of a bunch of individual changes: nir/builder: Generate 32-bit bool opcodes transparently nir/algebraic: Remap Boolean opcodes to the 32-bit variant Use 32-bit opcodes in the NIR producers and optimizations Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c Use 32-bit opcodes in the NIR back-ends Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Add support for MinLodJason Ekstrand2018-12-111-1/+11
| | | | Reviewed-by: Ian Romanick <[email protected]>
* nir: Make boolean conversions sized just like the othersJason Ekstrand2018-12-051-2/+2
| | | | | | | | | Instead of a single i2b and b2i, we now have i2b32 and b2iN where N is one if 8, 16, 32, or 64. This leads to having a few more opcodes but now everything is consistent and booleans aren't a weird special case anymore. Reviewed-by: Connor Abbott <[email protected]>
* spirv: add SpvCapabilityInt64AtomicsSamuel Pitoiset2018-12-051-1/+4
| | | | | | | Required for VK_KHR_shader_atomic_int64. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv/vtn: handle variable pointers without offset loweringDave Airlie2018-11-202-8/+10
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add alignment parameters to SSBO, UBO, and shared accessJason Ekstrand2018-11-152-0/+8
| | | | | | | | | | This also changes spirv_to_nir and glsl_to_nir to set them. The one place that doesn't set them is shared memory access lowering in nir_lower_io. That will have to be updated before any consumers of it can effectively use these new alignments. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Acked-by: Karol Herbst <[email protected]>
* nir/spirv: Force 32-bit for UBO and SSBO BooleansJason Ekstrand2018-11-151-2/+8
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* nir/builder: Add a nir_pack/unpack/bitcast helpersJason Ekstrand2018-11-151-76/+25
| | | | | | | | | The new helpers can generate any pack/unpack operation including those for which we do not have specific opcodes and they express a bitcast in terms of these pack/unpack operations. In particular, the new helpers properly handle 8-bit types. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* nir/builder: Add iadd_imm and imul_imm helpersJason Ekstrand2018-11-151-8/+6
| | | | | | | | | | The pattern of adding or multiplying an integer by an immediate is fairly common especially in deref chain handling. This adds a helper for it and uses it a few places. The advantage to the helper is that it automatically handles bit sizes for you. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Karol Herbst <[email protected]>
* nir/spirv: cast shift operand to u32Karol Herbst2018-11-142-0/+31
| | | | | | | | v2: fix for specialization constants as well Reviewed-by: Jason Ekstrand <[email protected]> Cc: [email protected] Signed-off-by: Karol Herbst <[email protected]>
* spirv: Pass SSA values through functionsJason Ekstrand2018-10-301-41/+139
| | | | | | | | Previously, we would create temporary variables and fill them out. Instead, we create as many function parameters as we need and pass them through as SSA defs. Reviewed-by: Iago Toral Quiroga <[email protected]>
* spirv: Initialize subgroup destinations with the destination typeJason Ekstrand2018-10-261-4/+8
| | | | | | | Instead of initializing them manually, just use the type that we already have sitting there. Reviewed-by: Ian Romanick <[email protected]>
* spirv: Use the right bit-size for spec constant opsJason Ekstrand2018-10-261-3/+9
| | | | | | | | | | | Previously, we would always pull the bit size from the destination which is wrong for opcodes like nir_ilt where the sources are variable-sized but the destination is a fixed size. We were getting lucky before because nir_op_ilt returns a 32-bit value and basically everyone who uses spec constants uses 32-bit ones. Cc: [email protected] Reviewed-by: Ian Romanick <[email protected]>
* nir/builder: Add a nir_imm_true/false helpersJason Ekstrand2018-10-262-7/+7
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* spirv: Add no-op support for VK_GOOGLE_hlsl_functionality1Jason Ekstrand2018-10-222-0/+12
| | | | | | | | | | | This extension adds two new decorations which carry meaning only for HLSL shaders. They are expected to be handled by higher level layers and can be ignored by implementations. However, it does save the client a bit of work if the implementation safely ignores them instead of the client having to strip them out of the SPIR-V in order for it to be valid. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Add support for SPV_GOOGLE_decorate_stringJason Ekstrand2018-10-221-0/+8
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Update SPIR-V json and headers to Khronos masterJason Ekstrand2018-10-132-13/+604
| | | | | | This corresponds to commit 801cca8104245c07e8cc532 on GitHub. Acked-by: Bas Nieuwenhuizen <[email protected]>
* spirv/nir: handle memory access qualifiers for SSBO loads/storesSamuel Pitoiset2018-10-123-12/+75
| | | | | | | | | | | v2: - change how the access qualifiers are accumulated v3: - duplicate members in struct_member_decoration_cb() - handle access qualifiers on variables - remove access qualifiers handling in _vtn_variable_load_store() - fix setting access qualifiers on type->array_element Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]
* spirv: mark variables decorated with XfbBuffer as always activeSamuel Pitoiset2018-10-051-0/+1
| | | | | | | | Otherwise, they are removed during NIR linking or in some lowering passes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Move function call handling to vtn_cfgJason Ekstrand2018-10-023-63/+65
| | | | | | | It makes way more sense for it to live there with the rest of function handling. Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Use a bitfield for image access qualifiersJason Ekstrand2018-08-291-5/+5
| | | | | | | | | | This commit expands the current memory access enum to contain the extra two bits provided for images. We choose to follow the SPIR-V convention of NonReadable and NonWriteable because readonly implies that you *can* read so readonly + writeonly doesn't make as much sense as NonReadable + NonWriteable. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Make image load/store intrinsics variable-widthJason Ekstrand2018-08-291-0/+2
| | | | | | | | | Instead of requiring 4 components, this allows them to potentially use fewer. Both the SPIR-V and GLSL paths still generate vec4 intrinsics so drivers which assume 4 components should be safe. However, we want to be able to shrink them for i965. Reviewed-by: Kenneth Graunke <[email protected]>
* spirv: Make VertexIndex and VertexId both non-zero-basedNeil Roberts2018-08-131-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GLSL has gl_VertexID which is supposed to be non-zero-based. SPIR-V has both VertexIndex and VertexId builtins whose meanings are defined by the APIs. Vulkan defines VertexIndex as being non-zero-based. In Vulkan VertexId and InstanceId have no meaning and are pretty much just reserved for OpenGL at this point. GL_ARB_spirv removes VertexIndex and defines VertexId to be the same as gl_VertexId (which is also non-zero-based). Previously in Mesa it was treating VertexIndex as non-zero-based and VertexId as zero-based, so it was breaking for GL. This behaviour was apparently based on Khronos bug 14255. However that bug doesn’t seem to have made a final decision for VertexId. Assuming there really is no other definition for VertexId for Vulkan it seems better to just make them both have the same value. v2: update comment and commit descriptions, based on Jason Ekstrand explanation of the meaning/rationale behind all those builtins (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: fill info.gs.input_primitive tooAlejandro Piñeiro2018-08-131-0/+2
| | | | | | | | | | | info.gs.output_primitive was already being filled. Not sure why this is not needed on Vulkan, but we found to be needed for ARB_gl_spirv. Specifically, this is needed to get the following test passing: KHR-GL45.gl_spirv.spirv_validation_builtin_variable_decorations_test Reviewed-by: Timothy Arceri <[email protected]>
* meson: Build with Python 3Mathieu Bridon2018-08-101-2/+2
| | | | | | | | | | | | Now that all the build scripts are compatible with both Python 2 and 3, we can flip the switch and tell Meson to use the latter. Since Meson already depends on Python 3 anyway, this means we don't need two different Python stacks to build Mesa. Signed-off-by: Mathieu Bridon <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* compiler/spirv: add XFB and GeometryStreams capability check supportAlejandro Piñeiro2018-07-311-2/+8
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* spirv/nir: Fix the stream ID when emitting a primitive or vertexNeil Roberts2018-07-311-2/+5
| | | | | | | | | It looks like it was previously taking the SPIR-V instruction number directly instead of looking up the constant value. v2: use vtn_constant_value helper (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Handle the SpvDecorationStream decorationNeil Roberts2018-07-312-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | From SPIR-V 1.0 spec, section 3.20, "Decoration": "Stream Apply to an object or a member of a structure type. Indicates the stream number to put an output on." Note the "or", so that means that it is allowed for both a full struct or a membef or a struct (although the wording is not really ideal, and somewhat error-prone, imho). We found this with some Geometry Streams tests for ARB_gl_spirv, where the full gl_PerVertex is assigned Stream 0 (default value on OpenGL for gl_PerVertex). So this commit allows structs to have this Decoration, and sets the stream at the nir variable if needed. Signed-off-by: Neil Roberts <[email protected]> Signed-off-by: Alejandro Piñeiro <[email protected]> v2: squash two Decoration Stream patches (Jason) Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* spirv: Handle XFB variable decorationsNeil Roberts2018-07-311-3/+9
| | | | | | | | | These set the new explicit XFB members on nir_variable. This is needed to support ARB_gl_spirv, as Vulkan doesn't support transform feedback. Reviewed-by: Timothy Arceri <[email protected]>
* spirv: Handle SpvExecutionModeXfbNeil Roberts2018-07-311-1/+1
| | | | | | This just sets has_transform_feedback_varyings on the shader. Reviewed-by: Timothy Arceri <[email protected]>
* nir: add builtin builderKarol Herbst2018-07-241-45/+13
| | | | | | | | | | | also move some of the GLSL builtins over we will need for implementing some OpenCL builtins v2: replace NIR_IMM_FP by nir_imm_floatN_t in ported code fix up changes caused by swizzle rework Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* nir/spirv: import OpenCL.std.hRob Clark2018-07-241-0/+211
| | | | | | | | | Lightly edited to be valid 'C' code. Is there a bug open to fix this upstream? Acked-by: Jason Ekstrand <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* spirv: add support for SPV_KHR_post_depth_coverageIlia Mirkin2018-07-221-0/+9
| | | | | | | | | Allow the capability to be exposed, and convert the new execution mode into fs state. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: initialize is_vertex_inputCaio Marcelo de Oliveira Filho2018-07-181-3/+1
| | | | | | | | | | | | | | | Fixes warning: ../../src/compiler/spirv/vtn_variables.c: In function ‘var_decoration_cb’: ../../src/compiler/spirv/vtn_variables.c:1400:12: warning: ‘is_vertex_input’ may be used uninitialized in this function [-Wmaybe-uninitialized] bool is_vertex_input; ^~~~~~~~~~~~~~~ The code used to set is_vertex_input in all possible codepaths, but after 23edc5b1ef3 "spirv: translate default-block uniforms" the compiler isn't sure all codepaths will initialize the variable. Reviewed-by: Anuj Phogat <[email protected]>
* nir/spirv: print id for unsupported alu opcodeKarol Herbst2018-07-171-1/+1
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* nir: prepare for bumping up max components to 16Karol Herbst2018-07-172-2/+2
| | | | | | | | | | | OpenCL knows vector of size 8 and 16. v2: rebased on master (nir_swizzle rework) rework more declarations with nir_component_mask_t adjust print_var_decl Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* spirv: Fix a couple of image atomic load/store bugsJason Ekstrand2018-07-161-17/+30
| | | | | | | | | | For one thing, the NIR opcodes for image load/store always take and return a vec4 value regardless of the image type. We need to fix up both the source and destination to handle it. For another thing, we weren't actually setting up a destination in the OpAtomicLoad case. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: [email protected]
* nir/spirv: implement BuiltInWorkDimRob Clark2018-07-151-0/+4
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
* nir/spirv: print id for unsupported builtinsKarol Herbst2018-07-151-1/+1
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Karol Herbst <[email protected]>
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