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* spirv: Add support for SPV_KHR_multiviewJason Ekstrand2017-05-033-0/+9
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Bump the SPIR-V header to the latest public versionJason Ekstrand2017-05-031-3/+31
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: consistently use ifndef guards over pragma onceEmil Velikov2017-03-223-2/+10
| | | | | | | Signed-off-by: Emil Velikov <[email protected]> Acked-by: Vedran Miletić <[email protected]> Acked-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* spirv: Implement IsInf using an integer comparisonJason Ekstrand2017-03-201-1/+1
| | | | | | | | | | | Since we already do fabs on the one source, we're guaranteed to get positive infinity if we get any infinity at all. Since +inf only has one IEEE 754 representation, we can use an integer comparison and avoid all of the ordered/unordered issues. Cc: Dave Airlie <[email protected]> Reviewed-by: Elie Tournier <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* nir: Make image_size a variable-width intrinsicJason Ekstrand2017-03-141-7/+11
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir/spirv: Restrict the number of channels in texture coordinatesJason Ekstrand2017-03-141-1/+2
| | | | | | | | | Some SPIR-V texturing instructions pack more than the texture coordinate into the coordinate source. We need to mask off the unused channels. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* spirv: Silence unused variable warnings in release modeJason Ekstrand2017-03-071-0/+1
| | | | Reviewed-by: Jordan Justen <[email protected]>
* spirv: Use nir_builder for control flowJason Ekstrand2017-03-011-31/+14
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* nir: Combine the int and double [un]pack opcodesJason Ekstrand2017-02-161-2/+2
| | | | | | | NIR is a typeless IR and the two opcodes, when considered bitwise, do exactly the same thing. There's no reason to have two versions. Reviewed-by: Kenneth Graunke <[email protected]>
* spirv: handle SpvOpUConvert in proper place.Dave Airlie2017-02-161-1/+1
| | | | | | | | This was falling into the quantizetof16 path. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* spirv: add support for Int64 capabilityDave Airlie2017-02-162-1/+4
| | | | | | | | This just adds the support at the spirv->nir level for the Int64 cap. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* spirv/nir: add support for int64Dave Airlie2017-02-162-2/+32
| | | | | | | This adds the spirv->nir conversion for int64 types. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* spirv: Add support for SpvCapabilityStorageImageReadWithoutFormat.Bas Nieuwenhuizen2017-02-152-1/+5
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* spirv: Add support for SpvCapabilityStorageImageWriteWithoutFormatAlex Smith2017-02-143-2/+9
| | | | | | | | | | | Allow that capability if the driver indicates that it is supported, and flag whether images are read-only/write-only in the nir_variable (based on the NonReadable and NonWritable decorations), which drivers may need to implement this. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/spirv: do not require a format with images that are not sampledIago Toral Quiroga2017-02-141-2/+0
| | | | | | | As soon as we support shaderStorageImageWriteWithoutFormat we can see write-only images (sampled == 2) that don't have a format specified. Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Add more asserts in vtn_vector_constructJason Ekstrand2017-02-071-0/+15
| | | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99465
* spirv: add SPV_KHR_shader_draw_parameters supportLionel Landwerlin2017-02-013-0/+17
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* nir/spirv/glsl450: Implement IEEE-compliant handling of atan2(±∞, ±∞).Francisco Jerez2017-01-311-1/+21
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Juan A. Suarez Romero <[email protected]>
* nir/spirv/glsl450: Rewrite atan2 implementation to fix accuracy and handling ↵Francisco Jerez2017-01-311-22/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of zero/infinity. See "glsl: Rewrite atan2 implementation to fix accuracy and handling of zero/infinity." for the rationale, but note that the instruction count benefit discussed there is somewhat less important for the SPIRV implementation, because the current code already emitted no control flow instructions -- Still this saves us one hardware instruction per scalar component on Intel SKL hardware. Fixes the following Vulkan CTS tests on Intel hardware: dEQP-VK.glsl.builtin.precision.atan2.highp_compute.scalar dEQP-VK.glsl.builtin.precision.atan2.highp_compute.vec2 dEQP-VK.glsl.builtin.precision.atan2.highp_compute.vec3 dEQP-VK.glsl.builtin.precision.atan2.highp_compute.vec4 dEQP-VK.glsl.builtin.precision.atan2.mediump_compute.vec2 dEQP-VK.glsl.builtin.precision.atan2.mediump_compute.vec4 Note that most of the test-cases above expect IEEE-compliant handling of atan2(±∞, ±∞), which this patch doesn't explicitly handle, so except for the last two the test-cases above weren't expected to pass yet. The reason they do is that the i965 back-end implementation of the NIR fmin and fmax instructions is not quite GLSL-compliant (it complies with IEEE 754 recommendations though), because fmin/fmax of a NaN and a non-NaN argument currently always return the non-NaN argument, which causes atan() to flush NaN to one and return the expected value. The front-end should probably not be relying on this behavior for correctness though because other back-ends are likely to behave differently -- A follow-up patch will handle the atan2(±∞, ±∞) corner cases explicitly. v2: Fix up argument scaling to take into account the range and precision of exotic FP24 hardware. Flip coordinate system for arguments along the vertical line as if they were on the left half-plane in order to avoid division by zero which may give unspecified results on non-GLSL 4.1-capable hardware. Sprinkle in some more comments. Reviewed-by: Ian Romanick <[email protected]>
* spirv: handle undefined components for OpVectorShuffleLionel Landwerlin2017-01-261-15/+38
| | | | | | | | | | Fixes: dEQP-VK.spirv_assembly.instruction.compute.opspecconstantop.vector_related dEQP-VK.spirv_assembly.instruction.graphics.opspecconstantop.vector_related* Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: "17.0 13.0" <[email protected]>
* spirv: handle OpUndef as part of the variable parsing passLionel Landwerlin2017-01-262-0/+7
| | | | | | | | | | | | | | | | | | | | | Looking at the following bit of SPIRV shader : ... %zero = OpConstant %i32 0 %ivec3_0 = OpConstantComposite %ivec3 %zero %zero %zero %vec3_undef = OpUndef %ivec3 %sc_0 = OpSpecConstant %i32 0 %sc_1 = OpSpecConstant %i32 0 %sc_2 = OpSpecConstant %i32 0 ... Our compiler currently stops parsing variables & types on the OpUndef and switches to instructions, leaving the following sc_[0-2] variables untreated. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: "17.0 13.0" <[email protected]>
* spirv: bump headers to SPIRV 1.1Lionel Landwerlin2017-01-253-9/+86
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add default handler for new enumsLionel Landwerlin2017-01-252-0/+15
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: fix typosLionel Landwerlin2017-01-251-3/+3
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: handle gl_SampleMaskIago Toral Quiroga2017-01-251-2/+6
| | | | | | | | | | | | | SPIR-V maps both gl_SampleMask and gl_SampleMaskIn to the same builtin (SampleMask). The only way to tell which one we are dealing with is to check if it is an input or an output. Fixes: dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.write.* Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* spirv: acknowledge multisampled input attachmentsIago Toral Quiroga2017-01-251-3/+8
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* spirv: don't assert with location decorations on non i/o variablesLionel Landwerlin2017-01-201-1/+2
| | | | | | | | | | Some applications might add location decoration to samplers. Rather than raising an error it seems it would make more sense to just discard these decorations. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: 17.0 <[email protected]>
* spirv: fix warn string typoLionel Landwerlin2017-01-201-1/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Handle patch decorations up-frontJason Ekstrand2017-01-121-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Once again, SPIR-V is insane... It allows you to place "patch" decorations on structure members. Presumably, this is so that you can do something such as out struct S { layout(location = 0) patch vec4 thing1; layout(location = 0) vec4 thing2; } str; And have your I/O "nicely" organized. While this is a bit silly, it's allowed and well-defined so whatever. Where it really gets interesting is when you have an array of struct. SPIR-V says nothing about not allowing you to have those qualifiers on the members of a struct that's inside an array and GLSLang does this. Specifically, if you have layout(location = 0) out patch struct S { vec4 thing1; vec4 thing2; } str[2]; then GLSLang will place the "patch" decorations on the struct members. This is ridiculous there is no way that having some of them be patch and some not would be well-defined given that patch and non-patch outputs are in effectively different storage classes. This commit moves around the way we handle the "patch" decoration so that we can detect even the crazy cases and handle them. Fixes: dEQP-VK.tessellation.user_defined_io.per_patch_block_array.* Reviewed-by: Kenneth Graunke <[email protected]>
* spirv: fix typo in warning messageIago Toral Quiroga2017-01-121-1/+1
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* spirv: Shut up unhandled enumeration value warnings.Kenneth Graunke2017-01-111-0/+2
| | | | | | We don't want to do anything for the other cases. Signed-off-by: Kenneth Graunke <[email protected]>
* spirv: gl_PrimitiveID in the fragment shader is handled as an inputIago Toral Quiroga2017-01-111-1/+4
| | | | | | | | | Geometry and Tessellation stages do handle this as a system value instead. Fixes: dEQP-VK.geometry.basic.primitive_id Reviewed-by: Dave Airlie <[email protected]>
* spirv: Silence unsupported tessellation capability warnings.Kenneth Graunke2017-01-102-2/+6
| | | | | | | | ...when the capability bit is set. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> [v1] Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Tidy some repeated if checks by using a switch statement.Kenneth Graunke2017-01-101-8/+9
| | | | | | | Iago suggested tidying this. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Add tessellation varying and built-in support.Kenneth Graunke2017-01-103-6/+52
| | | | | | | | | | | | We need to: - handle the extra array level for per-vertex varyings - handle the patch qualifier correctly - assign varying locations Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Handle tessellation execution modes.Kenneth Graunke2017-01-101-6/+41
| | | | | | | | | | v2: Use info->tess. v3: Handle more things in either TCS/TES. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Dave Airlie <[email protected]> [v1] Reviewed-by: Iago Toral Quiroga <[email protected]> [v1] Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Move cursor before calling vtn_ssa_value() in phi 2nd pass.Kenneth Graunke2017-01-091-1/+2
| | | | | | | | | | | | | | vtn_ssa_value() can produce variable loads, and the cursor might be after a return statement, causing nir_builder assert failures about not inserting instructions after a jump. This fixes: dEQP-VK.spirv_assembly.instruction.graphics.barrier.in_if dEQP-VK.spirv_assembly.instruction.graphics.barrier.in_switch Cc: "13.0 12.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: enable SpvCapabilityFloat64 only to supported platformsSamuel Iglesias Gonsálvez2017-01-092-1/+5
| | | | | | | | v2 (Jason): - Use nir_spirv_supported_extensions to check if the feature is enabled. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add support for doubles to OpSpecConstantSamuel Iglesias Gonsálvez2017-01-093-6/+47
| | | | | | | | | v2 (Jason): - Fix indent in radv change - Add vtn_u64_literal() helper to take 64 bits (Jason) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv/nir: add (un)packDouble2x32() translationSamuel Iglesias Gonsálvez2017-01-091-0/+2
| | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv/nir: implement DF conversionsSamuel Iglesias Gonsálvez2017-01-093-13/+23
| | | | | | | | SPIR-V does not have special opcodes for DF conversions. We need to identify them by checking the bit size of the operand and the result. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add support for doubles on OpComposite{Insert,Extract}Samuel Iglesias Gonsálvez2017-01-091-0/+1
| | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Enable double floating points when copying variables in ↵Samuel Iglesias Gonsálvez2017-01-091-0/+1
| | | | | | | _vtn_variable_copy() Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add double support to _vtn_block_load_store()Samuel Iglesias Gonsálvez2017-01-091-0/+1
| | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add double support to _vtn_variable_load_storeSamuel Iglesias Gonsálvez2017-01-091-0/+1
| | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add double support to SpvOpCompositeExtractSamuel Iglesias Gonsálvez2017-01-091-2/+14
| | | | | | | | v2 (Jason): - Add asserts. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with ↵Samuel Iglesias Gonsálvez2017-01-091-12/+40
| | | | | | | | | | | | | | | | | double-based vecs We need to pick two 32-bit values per component to perform the right shuffle operation. v2 (Jason): - Add assert to check matching bit sizes (Jason) - Simplify the code to pick components (Jason) v3: - Switch on bit_size once (Jason) - Add comment to explain the constant value for unused components (Erik) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add DF support to SpvOp*ConstantCompositeSamuel Iglesias Gonsálvez2017-01-091-3/+11
| | | | | | | | v2 (Jason): - Add assert. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add DF support to vtn_const_ssa_value()Samuel Iglesias Gonsálvez2017-01-091-3/+5
| | | | | Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: add support for loading DF constantsSamuel Iglesias Gonsálvez2017-01-091-2/+10
| | | | | | | | v2 (Jason): - Add assert. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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