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* compiler: fix typoEric Engestrom2017-11-281-1/+1
| | | | | Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* compiler: use NDEBUG to guard assertsEric Engestrom2017-11-283-6/+6
| | | | | | | | | nir_validate.c's #endif already had the correct NDEBUG comment Fixes: dcb1acdea00a8f2c29777 "nir/validate: Only build in debug mode" Fixes: 9ff71b649b4b3808a9e17 "i965/nir: Validate that NIR passes call nir_metadata_preserve()" Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* nir: fill outputs_read field and add patch outputs read (v2)Dave Airlie2017-11-271-12/+28
| | | | | | | | This is to be used for TCS optimisations on radv. v2: don't set written on reads (nha) Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
* nir: allow texture offsets with cube mapsIlia Mirkin2017-11-251-2/+13
| | | | | | | | | | GL doesn't have this, but some hardware supports it. This is convenient for lowering tg4 to plain texture calls, which is necessary on Adreno A4xx hardware. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Rob Clark <robdclark@gmail.com>
* nir/gather_info: recognize load_patch_vertices_in as a system valueIago Toral Quiroga2017-11-221-0/+1
| | | | | | | | This intrinsic is produced to load SYSTEM_VALUE_VERTICES_IN, which is generated to load gl_PatchVerticesIn in the SPIR-V path for both Vulkan and OpenGL. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* nir/spirv: tg4 requires a samplerAlex Smith2017-11-131-1/+0
| | | | | | | | | | Gather operations in both GLSL and SPIR-V require a sampler. Fixes gathers returning garbage when using separate texture/samplers (on AMD, was using an invalid sampler descriptor). Signed-off-by: Alex Smith <asmith@feralinteractive.com> Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: add streams to nir dataTimothy Arceri2017-11-121-0/+8
| | | | | | This will be used by gallium drivers. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* nir: handle get_buffer_size in nir_lower_atomics_to_ssboRob Clark2017-11-101-0/+1
| | | | | | | | | Overlooked initially, be we need to remap the SSBO index for this as well. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* nir: Don't print swizzles when there are more than 4 componentsMatt Turner2017-11-081-1/+1
| | | | | | | | | ... as can happen with various types like mat4, or else we'll smash the stack writing past the end of components_local[]. Fixes: 5a0d3e1129b7 ("nir: Print the components referenced for split or packed shader in/outs.") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: Validate base types on array dereferencesJason Ekstrand2017-11-071-2/+16
| | | | | | | | | We were already validating that the parent type goes along with the child type but we weren't actually validating that the parent type is reasonable. This fixes that. Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir,intel/compiler: Use a fixed subgroup sizeJason Ekstrand2017-11-072-24/+13
| | | | | | | | | | | | | | | | The GL_ARB_shader_ballot spec says that gl_SubGroupSizeARB is declared as a uniform. This means that it cannot change across an invocation such as a draw call or a compute dispatch. For compute shaders, we're ok because we only ever use one dispatch size. For fragment, however, the hardware dynamically chooses between SIMD8 and SIMD16 which violates the spec. Instead, let's just pick a subgroup size based on the shader stage. The fixed size we choose for compute shaders is a bit higher than strictly needed but there's no real harm in that. The advantage is that, if they do anything interesting with the value, NIR will see it as an immediate and can optimize better. Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir/lower_subgroups: Lower ballot intrinsics to the specified bit sizeJason Ekstrand2017-11-073-30/+83
| | | | | | | | | | | | | | Ballot intrinsics return a bitfield of subgroups. In GLSL and some SPIR-V extensions, they return a uint64_t. In SPV_KHR_shader_ballot, they return a uvec4. Also, some back-ends would rather pass around 32-bit values because it's easier than messing with 64-bit all the time. To solve this mess, we make nir_lower_subgroups take a new parameter called ballot_bit_size and it lowers whichever thing it gets in from the source language (uint64_t or uvec4) to a scalar with the specified number of bits. This replaces a chunk of the old lowering code. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir/builder: Add a nir_imm_intN_t helperJason Ekstrand2017-11-071-0/+12
| | | | | | | This lets you easily build integer immediates of arbitrary bit size. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
* nir/lower_system_values: Lower SUBGROUP_*_MASK based on typeJason Ekstrand2017-11-071-2/+3
| | | | | | | | | The SUBGROUP_*_MASK system values are uint64_t when coming in from GLSL but uvec4 when coming in from SPIR-V. Lowering based on type allows us to nicely handle both. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir: Make ballot intrinsics variable-sizeJason Ekstrand2017-11-072-6/+7
| | | | | | | | This way they can return either a uvec4 or a uint64_t. At the moment, this is a no-op since we still always return a uint64_t. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir: Add a ssa_dest_init_for_type helperJason Ekstrand2017-11-071-0/+9
| | | | | | | This would be useful a number of places Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir: Add a new subgroups lowering passJason Ekstrand2017-11-075-181/+200
| | | | | | | | | | | | This commit pulls nir_lower_read_invocations_to_scalar along with most of the guts of nir_opt_intrinsics (which mostly does subgroup lowering) into a new nir_lower_subgroups pass. There are various other bits of subgroup lowering that we're going to want to do so it makes a bit more sense to keep it all together in one pass. We also move it in i965 to happen after nir_lower_system_values to ensure that because we want to handle the subgroup mask system value intrinsics here. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* intel/cs: Push subgroup ID instead of base thread IDJason Ekstrand2017-11-071-3/+1
| | | | | | | | | | We're going to want subgroup ID for SPIR-V subgroups eventually anyway. We really only want to push one and calculate the other from it. It makes a bit more sense to push the subgroup ID because it's simpler to calculate and because it's a real API thing. The only advantage to pushing the base thread ID is to avoid a single SHL in the shader. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* intel/cs: Rework the way thread local ID is handledJason Ekstrand2017-11-071-0/+3
| | | | | | | | | | Previously, brw_nir_lower_intrinsics added the param and then emitted a load_uniform intrinsic to load it directly. This commit switches things over to use a specific NIR intrinsic for the thread id. The one thing I don't like about this approach is that we have to copy thread_local_id over to the new visitor in import_uniforms. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir: fix a typoGwan-gyeong Mun2017-11-061-1/+1
| | | | | Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
* nir/serialize: fix build with gcc 4.4.7Dave Airlie2017-11-031-19/+19
| | | | | | | I had to build on RHEL6 today, and noticed this. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* nir: skip lowering sampler if there is no dereferenceTimothy Arceri2017-11-031-1/+3
| | | | | | This avoids a crash on the output of nir_lower_bitmap(). Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* nir: add tess patch support to nir_remove_unused_varyings()Timothy Arceri2017-11-031-19/+42
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* nir: Add hooks for testing serializationJason Ekstrand2017-10-312-0/+36
| | | | | Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* nir: add serialization and deserializationConnor Abbott2017-10-313-0/+1246
| | | | | | | | | | | | | | | | | | | | v2 (Jason Ekstrand): - Various whitespace cleanups - Add helpers for reading/writing objects - Rework derefs - [de]serialize nir_shader::num_* - Fix uses of blob_reserve_bytes - Use a bitfield struct for packing tex_instr data v3: - Zero nir_variable struct on deserialization. (Jordan) - Allow nir_serialize.h to be included in C++. (Jordan) - Handle NULL info.name. (Jason) - Set info.name to NULL when name is NULL. (Jordan) Acked-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Acked-by: Jason Ekstrand <jason@jlekstrand.net>
* nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARBNeil Roberts2017-10-311-2/+22
| | | | | | | | | | | | | | | | | | Previously the values were calculated by just shifting ~0 by the invocation ID. This would end up including bits that are higher than gl_SubGroupSizeARB. The corresponding CTS test effectively requires that these high bits be zero so it was failing. There is a Piglit test as well but this appears to checking the wrong values so it passes. For the two greater-than bitmasks, this patch adds an extra mask with (~0>>(64-gl_SubGroupSizeARB)) to force these bits to zero. Fixes: KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680#c3 Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Neil Roberts <nroberts@igalia.com>
* nir: Make nir_gather_info collect a uses_fddx_fddy flag.Kenneth Graunke2017-10-291-0/+16
| | | | | | | | i965 turns fddx/fddy into their coarse/fine variants based on the ctx->Hint.FragmentShaderDerivative setting. It needs to know whether this can impact a shader in order to better guess NOS settings. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir/opt_intrinsics: Rework progressJason Ekstrand2017-10-251-5/+9
| | | | | | | | | This commit fixes two issues: First, we were returning false regardless of whether or not the function made progress. Second, we were calling nir_metadata_preserve far more often than needed; we only need to call it once per impl. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
* nir/lower_wpos_ytransform: Support system value intrinsicsJason Ekstrand2017-10-251-0/+4
| | | | Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
* nir: Zero nir_load_const_instr::value for valgrind & nir_serializeJordan Justen2017-10-251-1/+1
| | | | | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: Zero local_size const struct for valgrind & nir_serializeJordan Justen2017-10-251-0/+1
| | | | | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir/intrinsics: Set the correct num_indices for load_outputJason Ekstrand2017-10-251-1/+1
| | | | | | | Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* meson: extract out variable for nir_algebraic.pyRob Clark2017-10-241-0/+2
| | | | | | | | Also needed in freedreno/ir3. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
* nir: Print the components referenced for split or packed shader in/outs.Eric Anholt2017-10-201-1/+25
| | | | | | | | | | | | | | Having 4 variables all called "gl_in_TexCoord0@n" isn't very informative, much better to see: decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0 (VARYING_SLOT_VAR0.x, 1, 0) decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0@0 (VARYING_SLOT_VAR0.y, 1, 0) decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0@1 (VARYING_SLOT_VAR0.z, 1, 0) decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0@2 (VARYING_SLOT_VAR0.w, 1, 0) v2: Handle arrays and structs better (by Timothy) Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
* nir: Add a safety check that we don't remove dead I/O vars after lowering.Eric Anholt2017-10-201-4/+14
| | | | | | | | | The pass only looks at var load/store intrinsics, not input load/store intrinsics, so assert that we don't see the other type. v2: Adjust comment indentation. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-2022-48/+51
| | | | | | | | It's redundant with nir_shader::info::stage. Acked-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* nir: set default lod to texture opcodes that needed it but don't provide itSamuel Iglesias Gonsálvez2017-10-201-0/+13
| | | | | | | | | | | | v2: - Use helper to add a new source to the texture instruction. v3: - Use nir_tex_instr_src_index() to simplify the patch (Jason). Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: Add a helper for adding texture instruction sourcesJason Ekstrand2017-10-173-25/+28
| | | | Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
* nir: add component level support to remove_unused_io_vars()Timothy Arceri2017-10-161-16/+21
| | | | Reviewed-by: Eric Anholt <eric@anholt.net>
* nir: add variant of lower_io_to_scalar to be called earlierTimothy Arceri2017-10-162-0/+255
| | | | | | | | | | | This is intended to be called before nir_lower_io() so that we can do some linking optimisations with the results. It can also be used with drivers that don't use nir_lower_io() at all such as RADV. v2: pass mode mask rather than first and last stage integer. Reviewed-by: Eric Anholt <eric@anholt.net>
* nir: Get rid of the variable on vote intrinsicsJason Ekstrand2017-10-121-3/+3
| | | | | | | | This looks like a copy+paste error. They don't actually write into that variable as would be implied by putting the return there. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable@lists.freedesktop.org
* nir/opcodes: Fix constant-folding of ufind_msbJason Ekstrand2017-10-121-1/+1
| | | | | | | | | We didn't fold correctly in the case of 0x1 because we never let the loop counter hit 0. Switching it to bit >= 0 solves this problem. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Cc: mesa-stable@lists.freedesktop.org
* nir: Make nir_shader_gather_info() track texelFetch texture accesses.Kenneth Graunke2017-10-121-1/+13
| | | | | | | | For TGSI-based drivers, st_glsl_to_tgsi records this information. For NIR-based drivers, nir_shader_gather_info() will do so. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: bump loop unroll limit to 96.Dave Airlie2017-10-111-1/+3
| | | | | | | | | | | With the ssao demo from Vulkan demos: radv/rx480: 440->440fps anv/haswell: 24->34 fps The demo does a 0->32 loop across a ubo with 32 members. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* nir: Move vc4's alpha test lowering to core NIR.Eric Anholt2017-10-104-0/+139
| | | | | | | | | | | | | I've been doing this inside of vc4, but vc5 wants it as well and it may be useful for other drivers (Intel has a related path for pre-gen6 with MRT, and freedreno had a TGSI path for it at one point). This required defining a common enum for the standard comparison functions, but other lowering passes are likely to also want that enum. v2: Add to meson.build as well. Acked-by: Rob Clark <robdclark@gmail.com>
* meson: add nir_linking_helpers.c to libnirDylan Baker2017-10-091-0/+1
| | | | | | | This was missed in a rebase, and doesn't affect radv or anv, only i965. Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* meson: convert gtest to an internal dependencyDylan Baker2017-10-031-2/+2
| | | | | | | | | | | | In truth gtest is an external dependency that upstream expects you to "vendor" into your own tree. As such, it makes sense to treat it more like a dependency than an internal library, and collect it's requirements together in a dependency object. v2: - include with -isystem instead of setting compiler args (Eric) Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* meson: Add build Intel "anv" vulkan driverDylan Baker2017-09-271-0/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows building and installing the Intel "anv" Vulkan driver using meson and ninja, the driver has been tested against the CTS and has seems to pass the same series of tests (they both segfault when the CTS tries to run wayland wsi tests). There are still a mess of TODO, XXX, and FIXME comments in here. Those are mostly for meson bugs I'm trying to fix, or for additional things to implement for other drivers/features. I have configured all intermediate libraries and optional tools to not build by default, meaning they will only be built if they're pulled in as a dependency of a target that will actually be installed) this allows us to avoid massive if chains, while ensuring that only the bits that need to be built are. v2: - enable anv, x11, and wayland by default - add configure option to disable valgrind v3: - fix typo in meson_options (Nicholas) v4: - Remove dead code (Eric) - Remove change to generator that was from v0 (Eric) - replace if chain with loop (Eric) - Fix typos (Eric) - define HAVE_DLOPEN for both libdl and builtin dl cases (Eric) v5: - rebase on util string buffer implementation Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> (v4)
* nir: add some helpers for doing linkingTimothy Arceri2017-09-262-0/+150
| | | | | | | | | | | | | The initial helpers add support for removing unused varyings between stages. V2: - Moved the io mask helper function into this file rather than nir.h so it's not used elsewhere considering it doesn't handle all corner cases. - Use bitmask rather than hash table to handle tcs outputs (Ken) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* nir: add always_active_io to nir variableTimothy Arceri2017-09-261-0/+10
| | | | | | | | Will be used in nir link pass to decided if we can remove a varying or not. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>