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* broadcom/vc5: Don't annotate dumps with stale live intervals.Eric Anholt2018-03-194-2/+8
| | | | | As you're debugging register allocation, you may have changed the intervals and not recomputed yet. Just skip the dump in that case.
* broadcom/vc5: Add support for register spilling.Eric Anholt2018-03-194-11/+276
| | | | | | | | | | | | | | | Our register spilling support is nice to have since vc4 couldn't at all, but we're still very restricted due to needing to not spill during a TMU operation, or during the last segment of the program (which would be nice to spill a value of, when there's a long-lived value being passed through with little modification from the start to the end). We could do better by emitting unspills for the last-segment values just before the last thrsw, since the last segment is probably not the maximum interference area. Fixes GTF uniform_buffer_object_arrays_of_all_valid_basic_types and 3 others.
* broadcom/vc5: Remove redundant last_inst lookup.Eric Anholt2018-03-191-1/+0
| | | | The point was to get the MOV, which the MOV_dest already returned.
* broadcom/vc5: On QPU pack error, dump the instruction and return cleanly.Eric Anholt2018-03-191-1/+7
| | | | This is nice for debugging when you've made a bad instruction.
* broadcom/vc5: Add cursors to the compiler infrastructure, like NIR's.Eric Anholt2018-03-193-8/+73
| | | | | This will let me do lowering late in compilation using the same instruction builder as we use in nir_to_vir.
* broadcom/vc5: Move the umul macro to a header.Eric Anholt2018-03-192-8/+8
| | | | Anywhere we want to multiply, we probably want this.
* broadcom/vc5: Correct the arg count of TIDX/EIDX.Eric Anholt2018-03-191-2/+2
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* broadcom/vc5: Re-do live variables after removing thrsws.Eric Anholt2018-03-192-3/+14
| | | | Otherwise our start/ends ips won't line up with the actual instructions.
* broadcom/vc5: Add a QPU helper for instructions using the TLB.Eric Anholt2018-03-192-0/+23
| | | | This will be used for detecting last thread segment in register spilling.
* broadcom/vc5: Introduce v3d_qpu_reads_vpm()/v3d_qpu_writes_vpm().Eric Anholt2018-03-192-4/+35
| | | | | These helpers will be used in register spilling to determine where to add a last thrsw if needed, and might help refactor QPU scheduling.
* broadcom/vc5: The ldvpm signal also a case of using the VPM.Eric Anholt2018-03-191-0/+3
| | | | | The QPU scheduling code calling this function already separately checked this signal.
* broadcom/vc5: Extract v3d_qpu_writes_tmu() helper.Eric Anholt2018-03-193-6/+12
| | | | This will be reused in register spilling.
* nir: add lower_ldexp to nir compiler optionsTimothy Arceri2018-02-281-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* broadcom/vc5: Fix "hardwrae" typo in a field name in XML.Eric Anholt2018-02-052-2/+2
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* broadcom/vc5: Try to merge more than 2 QPU instructions together.Eric Anholt2018-02-051-5/+13
| | | | | | | | Obviously it would be good to have an ADD and a MUL and a signal together, but we can even potentially have multiple signals merged, as well. total instructions in shared programs: 100423 -> 97874 (-2.54%) instructions in affected programs: 78812 -> 76263 (-3.23%)
* broadcom/vc5: Remove no-op MOVs after register allocation.Eric Anholt2018-02-051-1/+60
| | | | | | | | We emit some MOVs to track lifetimes of payload registers, but we don't need there to be actual MOV instructions for them. total instructions in shared programs: 101045 -> 100423 (-0.62%) instructions in affected programs: 37083 -> 36461 (-1.68%)
* broadcom/vc5: Add missing shader-db instruction counting.Eric Anholt2018-02-051-0/+7
| | | | I must have misplaced it in the instruction packing rework.
* broadcom/vc5: Fix a segfault on mix of booleans.Eric Anholt2018-02-011-1/+3
| | | | We don't have a src1 to look up if the compare instruction is "i2b".
* nir: add lower_all_io_to_temps flagTimothy Arceri2018-01-311-0/+1
| | | | | | | This will be used for freedreno and vc4 which require all inputs and outputs to be copied to temps. Reviewed-by: Marek Olšák <[email protected]>
* broadcom/vc5: Enable CLIF dumping of V3D 4.2.Eric Anholt2018-01-273-1/+10
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* broadcom/vc5: Update the compiler for V3D 4.2.Eric Anholt2018-01-271-2/+6
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* broadcom/vc5: Update QPU instruction pack/unpack for v4.2.Eric Anholt2018-01-274-5/+9
| | | | | After the 4.1 spec, 4.2 retroactively renamed patchid to barrierid because it's used for other barriers in compute.
* broadcom/vc5: Add XML for V3D 4.2.Eric Anholt2018-01-276-0/+1065
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* broadcom/vc5: Fix a race between XML codegen build and CLIF build.Eric Anholt2018-01-271-1/+4
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* Android: Attempt to fix broadcom build after vc5 changes.Eric Anholt2018-01-271-0/+5
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* autotools: include meson build files in tarballDylan Baker2018-01-191-1/+6
| | | | | | | | | | | | This adds the meson.build, meson_options.txt, and a few scripts that are used exclusively by the meson build. v2: - Remove accidentally included changes needed to test make dist with LLVM > 3.9 Signed-off-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* broadcom: add missing headers to the tarballEmil Velikov2018-01-181-2/+5
| | | | Signed-off-by: Emil Velikov <[email protected]>
* broadcom/vc5: Use MSF to ignore discards/non-dispatched channels in loops.Eric Anholt2018-01-121-1/+5
| | | | | Prevents potential infinite loops when a non-dispatched or discarded channel never triggers the loop break condition.
* broadcom/vc5: Use XOR instead of SUB for execute flags comparisons.Eric Anholt2018-01-121-3/+3
| | | | | I think this should be equivalent other than power, and it's the kind of comparison we use for nir_op_ieq.
* broadcom/vc5: Also check the update flags for avoiding DCE.Eric Anholt2018-01-121-1/+5
| | | | I was trying to do a NULL-destination UF, and it got removed.
* broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.Eric Anholt2018-01-121-3/+3
| | | | | Now that the actions are reused for centroid and nonperspective, give them a more generic name.
* broadcom/vc5: Add support for loading varyings in V3D 4.1.Eric Anholt2018-01-126-17/+13
| | | | | | | The LDVARY signal now writes an arbitrary register, so I took out the magic src register file and replaced it with an instruction with LDVARY set so we have somewhere to hang a QFILE_TEMP destination for register allocation.
* broadcom/vc5: Add compiler support for V3D 4.x texturing.Eric Anholt2018-01-127-6/+283
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* broadcom/vc5: Add the new TMU write addresses for V3D 4.x (and r5rep).Eric Anholt2018-01-122-10/+37
| | | | | | The V3D 3.x series of TMU writes with meaning depending on the texture type is replaced with writes to specific registers for each texture argument semantic.
* broadcom/vc5: Move V3D 3.3 texturing to a separate file.Eric Anholt2018-01-125-229/+267
| | | | | V3D 4.x texturing changes enough that #ifdefs would just make a mess of it.
* broadcom/vc5: Move V3D 3.3 VPM write setup to a separate file.Eric Anholt2018-01-125-34/+82
| | | | | For V4.1 texturing, I need the V4.1 XML, so the main compiler needs to stop including V3.3 XML.
* broadcom/vc5: Add support for V3D 4.1 CLIF dumping.Eric Anholt2018-01-125-17/+57
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* broadcom/vc5: Move the body of CLIF dumping to a per-version file.Eric Anholt2018-01-126-155/+255
| | | | | I want the library's entrypoints to still be unversioned, but the actual packet dumping needs to be per-version.
* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-128-78/+285
| | | | | This is a major performance boost on all of V3D, but is required on V3D 4.x where shaders are always either 2- or 4-threaded.
* broadcom/vc5: Properly schedule the thread-end THRSW.Eric Anholt2018-01-122-39/+137
| | | | | | | | | | This fills in the delay slots of thread end as much as we can (other than being cautious about potential TLBZ writes). In the process, I moved the thread end THRSW instruction creation to the scheduler. Once we start emitting THRSWs in the shader, we need to schedule the thread-end one differently from other THRSWs, so having it in there makes that easy.
* broadcom/vc5: Implement GFXH-1684 workaround.Eric Anholt2018-01-124-0/+20
| | | | Apparently the VPM writes need to be flushed out before we end the shader.
* broadcom/vc5: Add a test for .ifb in ADD ops.Eric Anholt2018-01-121-0/+1
| | | | | I had a .ifb being decoded weird in sampid, so this is to check that .ifb is fine.
* broadcom/vc5: Add the new tesselation opcodes in V3D 4.1.Eric Anholt2018-01-122-1/+5
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* broadcom/vc5: Use a physical-reg-only register class for LDVPM.Eric Anholt2018-01-122-8/+21
| | | | | This is needed for LDVPM on V3D 4.x, but will also be needed for keeping values out of the accumulators across THRSW.
* broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.Eric Anholt2018-01-129-51/+197
| | | | | | | | | | | Now, instead of a magic write register for VPM stores we have an instruction to do them (which means no packing of other ALU ops into it), with the ability to reorder the VPM stores due to the offset being baked into the instruction. VPM loads also gain the ability to be reordered by packing the row into the A argument. They also no longer write to the r3 accumulator, and instead must be stored to a physical register.
* broadcom/vc5: Drop dead VC5_QPU_* defines from qpu_instr.c.Eric Anholt2018-01-121-80/+0
| | | | | I had all the packing code in this file at one point, but these defines now live in qpu_pack.c.
* broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates.Eric Anholt2018-01-124-1/+94
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* broadcom/vc5: Drop signal bit #defines.Eric Anholt2018-01-122-8/+0
| | | | Signals are more complicated than that, and tables ended up being better.
* broadcom/vc5: Add support for V3Dv4 signal bits.Eric Anholt2018-01-1212-45/+322
| | | | | | | The WRTMUC replaces the implicit uniform loads in the first two texture instructions. LDVPM disappears in favor of an ALU op. LDVARY, LDTMU, LDTLB, and LDUNIF*RF now write to arbitrary registers, which required passing the devinfo through to a few more functions.
* broadcom/vc5: Fix pack/unpack of vfmul input unpack flags.Eric Anholt2018-01-122-0/+40
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