summaryrefslogtreecommitdiffstats
path: root/src/broadcom
Commit message (Expand)AuthorAgeFilesLines
* v3d: Add support for CS workgroup/invocation id intrinsics.Eric Anholt2019-01-145-1/+67
* v3d: Add support for shader_image_load_store.Eric Anholt2019-01-148-3/+652
* v3d: Add SSBO/atomic counters support.Eric Anholt2019-01-143-6/+143
* v3d: Add support for matrix inputs to the FS.Eric Anholt2019-01-141-13/+14
* v3d: Fix txf_ms 2D_ARRAY array index.Eric Anholt2019-01-141-8/+10
* v3d: Add support for the early_fragment_tests flag.Eric Anholt2019-01-141-0/+10
* v3d: Add support for flushing dirty TMU data at job end.Eric Anholt2019-01-141-0/+23
* nir: Add nir_lower_tex support for Broadcom's swizzled TG4 results.Eric Anholt2019-01-081-0/+2
* v3d: Use the core tex lowering.Eric Anholt2019-01-043-123/+10
* v3d: Stop scalarizing our uniform loads.Eric Anholt2019-01-042-102/+57
* v3d: Do UBO loads a vector at a time.Eric Anholt2019-01-042-35/+99
* v3d: Remove dead switch cases and comments from v3d_nir_lower_io.Eric Anholt2019-01-041-8/+3
* v3d: Reinstate the new shader-db output after v3d_compile() refactor.Eric Anholt2019-01-041-1/+18
* v3d: Refactor compiler entrypoints.Eric Anholt2019-01-022-163/+164
* v3d: Handle dynamically uniform IF statements with uniform control flow.Eric Anholt2019-01-021-1/+65
* v3d: Fold comparisons for IF conditions into the flags for the IF.Eric Anholt2019-01-025-12/+57
* v3d: Don't try to fold non-SSA-src comparisons into bcsels.Eric Anholt2019-01-021-1/+17
* v3d: Move the "Find the ALU instruction generating our bool" out of bcsel.Eric Anholt2019-01-021-6/+9
* v3d: Simplify the emission of comparisons for the bcsel optimization.Eric Anholt2019-01-021-37/+24
* v3d: Add support for gl_HelperInvocation.Eric Anholt2018-12-301-0/+8
* v3d: Add support for textureSize() on MSAA textures.Eric Anholt2018-12-301-0/+1
* v3d: Add support for non-constant texture offsets.Eric Anholt2018-12-301-8/+24
* v3d: Force sampling from base level for tg4.Eric Anholt2018-12-301-3/+3
* v3d: Add a note for a potential performance win on multop/umul24.Eric Anholt2018-12-301-0/+4
* v3d: Dead-code eliminate unused flags updates.Eric Anholt2018-12-301-4/+42
* v3d: Don't generate temps for comparisons.Eric Anholt2018-12-301-12/+14
* v3d: Move "does this instruction have flags" from sched to generic helpers.Eric Anholt2018-12-306-55/+48
* v3d: Drop incorrect dependency for flpop.Eric Anholt2018-12-301-4/+0
* v3d: Drop unused count_nir_instrs() helper.Eric Anholt2018-12-301-18/+0
* v3d: Hook up some shader-db output to GL_ARB_debug_output.Eric Anholt2018-12-303-2/+43
* v3d: Add a "precompile" debug flag for shader-db.Eric Anholt2018-12-292-0/+2
* v3d: Fix uniform pretty printing assertion failure with branches.Eric Anholt2018-12-291-0/+3
* v3d: Drop shadow comparison state from shader variant key.Eric Anholt2018-12-201-2/+0
* v3d: Add a fallthrough path for utile load/store of 32 byte lines.Eric Anholt2018-12-191-12/+16
* vc4: Move the utile load/store functions to a header for reuse by v3d.Eric Anholt2018-12-192-0/+223
* nir/opt_peephole_select: Don't peephole_select expensive math instructionsIan Romanick2018-12-171-1/+1
* nir/opt_peephole_select: Don't try to remove flow control around indirect loadsIan Romanick2018-12-171-1/+1
* v3d: Fix the argument type for vir_BRANCH().Eric Anholt2018-12-171-1/+1
* nir: Add a bool to int32 lowering passJason Ekstrand2018-12-161-0/+2
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-161-22/+22
* v3d: Use the original bit size when scalarizing uniform loads.Eric Anholt2018-12-161-1/+2
* v3d: Drop in a bunch of notes about performance improvement opportunities.Eric Anholt2018-12-143-1/+61
* v3d: Do uniform pretty-printing in the QPU dump.Eric Anholt2018-12-143-1/+62
* v3d: Move uniform pretty-printing to its own helper function.Eric Anholt2018-12-142-71/+77
* v3d: Avoid assertion failures when removing end-of-shader instructions.Eric Anholt2018-12-141-0/+6
* v3d: Add support for draw indirect for GLES3.1.Eric Anholt2018-12-141-0/+39
* v3d: Add missing flagging of SYNCB as a TSY op.Eric Anholt2018-12-141-0/+1
* v3d: Make sure that a thrsw doesn't split a multop from its umul24.Eric Anholt2018-12-141-0/+1
* v3d: Fix a leak of the disassembled instruction string during debug dumps.Eric Anholt2018-12-071-0/+1
* v3d: Add VIR dumping of TMU config p0/p1.Eric Anholt2018-12-072-0/+27
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 11:57:30 +0000