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* broadcom/vc5: Remove unused v3d_compiler.cAndreas Boll2017-11-081-43/+0
| | | | | | | | | | | Unused since original import of VC5. Fixes: ade416d0236 ("broadcom: Add VC5 NIR compiler.") Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* broadcom/vc5: Do 16-bit unpacking of integer texture returns properly.Eric Anholt2017-11-071-8/+29
| | | | | We were doing f16 unpacks, which trashed "1" values. Fixes many piglit texwrap GL_EXT_texture_integer cases.
* broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.Eric Anholt2017-11-072-5/+33
| | | | | | | The v3d_qpu_writes_r*() were only checking for fixed-function accumulator writes, not normal ALU writes to those regs. Fixes fs-discard-exit-2 on simulation (but not HW).
* broadcom/vc5: Add occlusion query support.Eric Anholt2017-11-071-0/+4
| | | | Fixes all of piglit's OQ tests.
* broadcom/vc5: Fix mipmap filtering enums.Eric Anholt2017-11-071-2/+24
| | | | | | | | The ordering of the values was even less obvious than I thought, with both the mip filter and the min filter being in different bits depending on whether the mip filter is none. Fixes piglit fs-textureLod-miplevels.shader_test
* broadcom/vc5: Fix missing enum decode for indexed primitives.Eric Anholt2017-11-071-2/+1
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* broadcom/vc5: Drop padding bits from the bottom of the TSDA address.Eric Anholt2017-11-071-1/+1
| | | | Fixes misaligned-looking addresses in decode.
* broadcom/genxml: Fix decoding of groups with small fields.Kenneth Graunke2017-11-071-2/+4
| | | | | | | | | | | | | | | | | Groups containing fields smaller than a byte probably not being decoded correctly. For example: <group count="32" start="32" size="4"> <field name="Vertex Element Enables" start="0" end="3" type="uint"/> </group> gen_field_iterator_next would properly walk over each element of the array, incrementing group_iter. However, the code to print the actual values only considered iter->field->start/end, which are 0 and 3 in the above example. So it would always fetch bits 3:0 of the current byte, printing the same value over and over. Cc: Eric Anholt <[email protected]>
* broadcom/vc5: Add some comments about the texture/output format ordering.Eric Anholt2017-10-301-7/+15
| | | | | | | | The output formats are consistent with their channels appearing from low to high in their name. Textures are interpreted the same way, but their names may have the channels swapped around. I'm retaining the texture names so that we are consistent with the documentation, but I want to leave a warning for others.
* broadcom/vc5: Stop lowering negates to subs.Eric Anholt2017-10-301-1/+8
| | | | | | | | In the case of fneg(0.0), we were getting back 0.0 instead of -0.0. We were also needing an immediate 0 value for ineg, when there's an opcode to do the job properly. Fixes fs-floatBitsToInt-neg.shader_test.
* broadcom/vc5: Add lowering for txf_ms to a txf on a 2x2-scaled texture.Eric Anholt2017-10-305-2/+96
| | | | | | | | | The HW has no native sampler support for multisample textures, but since we only need to support txf_ms and the layout is UIF, we just need to scale up the texcoords and then add in the sample. This drops the old TEXTURE_MSAA_ADDR special uniform, since we're treating MSAA textures as textures, rather than basically texbos like VC4 had to.
* broadcom/vc5: Keep output height pad out of the store TLB general address.Eric Anholt2017-10-301-1/+1
| | | | The equivalent load already had the pad separated out.
* broadcom/vc5: Drop padding bits from the texture shader state's address.Eric Anholt2017-10-301-1/+1
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* broadcom/vc5: Drop alignment bits from texture P1's address.Eric Anholt2017-10-301-1/+1
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* broadcom/vc5: Drop alignment bits from Z/S rendering mode config address.Eric Anholt2017-10-301-1/+1
| | | | Improves CLIF dumping output.
* broadcom/xml: Fix address packing for address with >= 8 alignment bits.Eric Anholt2017-10-301-2/+5
| | | | | | | We were handing the intra-byte padding fine, but with a 24-bit address (bottom 8 bits implied 0) we would end up off by 8 bytes in our shift, impacting vc5's load/store general packets (all other packets we have had <8 bits of padding).
* broadcom/clif: Print out the contents of the generic tile list.Eric Anholt2017-10-301-0/+19
| | | | This is the real meat of the RCL, so let's get it printed again.
* broadcom/clif: Move the CL printing part of CL dumps to a helper.Eric Anholt2017-10-301-28/+32
| | | | This will let me reuse the printing for processing branches to other CLs.
* broadcom/vc5: Lower unpack_*_4x8 to normal math.Eric Anholt2017-10-301-0/+3
| | | | | | We only have 2x16 unpacking in our ALUs. To enable this, we also need lower_fdiv for its new instructions, which had been handled at a higher level previously.
* broadcom/vc5: Add PIPE_TEX_WRAP_CLAMP support for linear-filtered textures.Eric Anholt2017-10-302-2/+10
| | | | | | I already had the texture's wrapping set up to use different behavior for nearest or linear, so we just needed to saturate the coordinates in linear mode to get the "proper" blend between the edge and border values.
* broadcom/xml: Throw an #error in XML-based codegen for a >1bit boolEric Anholt2017-10-301-0/+3
| | | | | I've debugged two nasty errors now due to copy-and-pasting a bool type when writing a uint field. Make sure I don't do that again.
* broadcom/vc4: Fix bool marking on Rasterizer Oversample Mode.Eric Anholt2017-10-301-1/+1
| | | | | We don't set this field using the XML codegen, but this would help us decode the right value in case of 16x (VG) oversampling.
* broadcom/vc5: Mark lookup type as uint, not bool.Eric Anholt2017-10-301-1/+1
| | | | Fixes non-2D texturing.
* meson: Fix vc5 deps on the XML-generated headers.Eric Anholt2017-10-202-2/+2
| | | | | I typoed and was depending on v3d_xml.h (the gzipped xml)_, not on the v3d_packet_v33_pack.h that the compiler and QPU packing actually use.
* broadcom/vc5: Propagate vc4 aliasing fix to vc5.Eric Anholt2017-10-201-1/+1
| | | | See e5fea0d621af2b14cf6c5e364eeaf293db460f2a
* broadcom/vc5: Use SETMSF to handle discards.Eric Anholt2017-10-202-25/+12
| | | | | | | | A bit of spec text suggested that (like vc4) condition codes should be used for discards, and the simulator was fine with it, but the 7268 disagrees and you have to use SETMSF instead or the color comes through. Fixes glsl-fs-discard-01 and many of the interpolation-with-clipping tests.
* broadcom/vc5: Set the snorm/unorm packing functions to be lowered.Eric Anholt2017-10-201-0/+4
| | | | | | We don't have native instructions for them, so set up the lowering. Once we support the bfi instructions that get generated, they should start actually working.
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-203-11/+11
| | | | | | | | It's redundant with nir_shader::info::stage. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* meson: Add support for the vc5 driver.Eric Anholt2017-10-173-0/+104
| | | | | | | v2: Default vc5 to off, since it requires the simulator currently. Add missing dep on the XML generation from libbroadcom_vc5. Reviewed-by: Dylan Baker <[email protected]> (v1)
* meson: Add support for the vc4 driver.Eric Anholt2017-10-172-0/+82
| | | | Reviewed-by: Dylan Baker <[email protected]>
* broadcom/vc5: Don't pair VPMSETUP with other peripheral access.Eric Anholt2017-10-121-0/+3
| | | | | The specs don't say you can't, but pairing it with an SFU write on the 7268 breaks all our simple shader tests using gl_MVP * gl_Vertex.
* broadcom/vc5: Fix inclusion of FS flag bits in dumping the FS address.Eric Anholt2017-10-121-1/+1
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* braodcom/vc5: Set up clear color for higher-bpp formats.Eric Anholt2017-10-101-0/+20
| | | | Fixes arb_color_buffer_float-clear
* broadcom/vc5: Fix Rendering Mode Common Config's color store bitmask.Eric Anholt2017-10-101-1/+1
| | | | | This controls the RTs that get stored by the default resolved store, the same way that the extended resolved store packet has a RT bitmask.
* broadcom/vc5: Add support for f32 render targets.Eric Anholt2017-10-102-13/+34
| | | | | The TLB write code is getting ugly and needs a refactoring (that will hopefully handle TLBU uniform coalescing as well).
* broadcom/vc5: Start hooking up multiple render targets support.Eric Anholt2017-10-102-14/+39
| | | | We now emit as many TLB color writes as there are color buffers.
* broadcom/vc5: Add support for GL_EXT_provoking_vertex.Eric Anholt2017-10-101-0/+1
| | | | | The bit was missing from the spec, but it's there in the simulator. Fixes the piglit clipflat test.
* broadcom/vc5: Mark our primitives as needing TF processing.Eric Anholt2017-10-101-0/+7
| | | | | The TF enable state appears to stick around until the next TF enable packet is sent, so we only want to request TF when the shader is using it.
* broadcom/vc5: Fix setup of TF dword output count.Eric Anholt2017-10-101-1/+1
| | | | I missed the "- 1" when reading the spec.
* broadcom/vc5: Fix handling of interp qualifiers on builtin color inputs.Eric Anholt2017-10-103-17/+28
| | | | | The interpolation qualifier, if specified, is supposed to take precedence over glShadeModel().
* broadcom/vc5: Fix CLIF dumping of lists that aren't capped by a HALT.Eric Anholt2017-10-102-8/+21
| | | | | | | The HW will halt when you hit a HALT packet, or when you hit the end address. Tell CLIF if there's an end address is so that it can stop correctly. (There was usually a 0 byte after the CL, so it would stop anyway).
* broadcom/vc5: Fix depth and stencil clear values.Eric Anholt2017-10-101-1/+1
| | | | | I had misread the packet description: We always have a 32f depth, and a separate u8 stencil.
* broadcom/compiler: Set up passthrough Z when doing FS discards.Eric Anholt2017-10-103-2/+15
| | | | | | | | In order to keep early-Z from writing early in a discard shader, you need to set the "modifies Z" bit in the shader state (which the new prog_data.discards will indicate). Then, in the shader we do a TLB write to make Z passthrough happen (the QPU result is ignored, so we use a NULL source).
* broadcom/compiler: Don't forget the discard state on TLB Z writes.Eric Anholt2017-10-101-0/+1
| | | | We don't want to write Z for discarded fragments.
* broadcom/compiler: Use defines instead of magic values in TLB write setup.Eric Anholt2017-10-101-6/+33
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* broadcom/xml: Add the vc5 Base Vertex/Base Instance packet.Eric Anholt2017-10-101-0/+6
| | | | This lets us do index_bias and ARB_base_instance.
* broadcom/xml: Add a bunch more vc5 tile list management packets.Eric Anholt2017-10-101-0/+60
| | | | We're going to need these for MSAA, and to use the generic per-tile list.
* broadcom/xml: Remove vc5 base packet for tile bin/render mode config.Eric Anholt2017-10-101-10/+0
| | | | | | These existed so I could unpack just the sub-id field to switch on in the old manual CLIF dumper. The new codegen handles sub-id automatically, but only if these stub packets aren't there with an implicit sub-id=0.
* braodcom/xml: Fix a pasteo in vc5 store tile buffer general.Eric Anholt2017-10-101-1/+1
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* broadcom: Add VC5 NIR compiler.Eric Anholt2017-10-1017-0/+7498
| | | | | | | | | | | This is a pretty straightforward fork of VC4's NIR compiler to VC5. The condition codes, registers, and I/O have all changed, making the backend hard to share, though their heritage is still recognizable. v2: Move to src/broadcom/compiler to match intel's layout, rename more "vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts with vc4, use new v3d_debug header, add compiler init/free functions, do texture swizzling in NIR to allow optimization.
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