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* broadcom/vc5: Add the new TMU write addresses for V3D 4.x (and r5rep).Eric Anholt2018-01-122-10/+37
| | | | | | The V3D 3.x series of TMU writes with meaning depending on the texture type is replaced with writes to specific registers for each texture argument semantic.
* broadcom/vc5: Move V3D 3.3 texturing to a separate file.Eric Anholt2018-01-125-229/+267
| | | | | V3D 4.x texturing changes enough that #ifdefs would just make a mess of it.
* broadcom/vc5: Move V3D 3.3 VPM write setup to a separate file.Eric Anholt2018-01-125-34/+82
| | | | | For V4.1 texturing, I need the V4.1 XML, so the main compiler needs to stop including V3.3 XML.
* broadcom/vc5: Add support for V3D 4.1 CLIF dumping.Eric Anholt2018-01-125-17/+57
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* broadcom/vc5: Move the body of CLIF dumping to a per-version file.Eric Anholt2018-01-126-155/+255
| | | | | I want the library's entrypoints to still be unversioned, but the actual packet dumping needs to be per-version.
* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-128-78/+285
| | | | | This is a major performance boost on all of V3D, but is required on V3D 4.x where shaders are always either 2- or 4-threaded.
* broadcom/vc5: Properly schedule the thread-end THRSW.Eric Anholt2018-01-122-39/+137
| | | | | | | | | | This fills in the delay slots of thread end as much as we can (other than being cautious about potential TLBZ writes). In the process, I moved the thread end THRSW instruction creation to the scheduler. Once we start emitting THRSWs in the shader, we need to schedule the thread-end one differently from other THRSWs, so having it in there makes that easy.
* broadcom/vc5: Implement GFXH-1684 workaround.Eric Anholt2018-01-124-0/+20
| | | | Apparently the VPM writes need to be flushed out before we end the shader.
* broadcom/vc5: Add a test for .ifb in ADD ops.Eric Anholt2018-01-121-0/+1
| | | | | I had a .ifb being decoded weird in sampid, so this is to check that .ifb is fine.
* broadcom/vc5: Add the new tesselation opcodes in V3D 4.1.Eric Anholt2018-01-122-1/+5
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* broadcom/vc5: Use a physical-reg-only register class for LDVPM.Eric Anholt2018-01-122-8/+21
| | | | | This is needed for LDVPM on V3D 4.x, but will also be needed for keeping values out of the accumulators across THRSW.
* broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.Eric Anholt2018-01-129-51/+197
| | | | | | | | | | | Now, instead of a magic write register for VPM stores we have an instruction to do them (which means no packing of other ALU ops into it), with the ability to reorder the VPM stores due to the offset being baked into the instruction. VPM loads also gain the ability to be reordered by packing the row into the A argument. They also no longer write to the r3 accumulator, and instead must be stored to a physical register.
* broadcom/vc5: Drop dead VC5_QPU_* defines from qpu_instr.c.Eric Anholt2018-01-121-80/+0
| | | | | I had all the packing code in this file at one point, but these defines now live in qpu_pack.c.
* broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates.Eric Anholt2018-01-124-1/+94
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* broadcom/vc5: Drop signal bit #defines.Eric Anholt2018-01-122-8/+0
| | | | Signals are more complicated than that, and tables ended up being better.
* broadcom/vc5: Add support for V3Dv4 signal bits.Eric Anholt2018-01-1212-45/+322
| | | | | | | The WRTMUC replaces the implicit uniform loads in the first two texture instructions. LDVPM disappears in favor of an ALU op. LDVARY, LDTMU, LDTLB, and LDUNIF*RF now write to arbitrary registers, which required passing the devinfo through to a few more functions.
* broadcom/vc5: Fix pack/unpack of vfmul input unpack flags.Eric Anholt2018-01-122-0/+40
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* broadcom/vc5: Introduce v3dx_macros.h and v3dx_pack.h headers.Eric Anholt2018-01-123-1/+88
| | | | | This will be used by vc5 for prefixing functions and including the pack header in v3d-version-dependent code, following the model of anv.
* broadcom/cle: Fix error path of missing a "type" in the XML.Eric Anholt2018-01-121-1/+2
| | | | | | We try to emit a #error and continue so that you can debug the missing type at C compile time, but were missing a couple of definitions in that path (sigh, python).
* broadcom/vc5: Add XML for V3D v4.1 (BCM7278)Eric Anholt2018-01-123-1/+1054
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* meson: Use dependencies for nirDylan Baker2018-01-111-2/+2
| | | | | | | | | | | | | | | | | This creates two new internal dependencies, idep_nir_headers and idep_nir. The former encapsulates the generation of nir_opcodes.h and nir_builder_opcodes.h and adding src/compiler/nir as an include path. This ensures that any target that needs nir headers will have the includes and that the generated headers will be generated before the target is build. The second, idep_nir, includes the first and additionally links to libnir. This is intended to make it easier to avoid race conditions in the build when using nir, since the number of consumers for libnir and it's headers are quite high. Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* meson: don't use intermediate variables that are immediately discardedDylan Baker2018-01-111-2/+1
| | | | | | | | | | | | | | | | For things like: loop x = func() list += x end just do: loop list += func() end Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* meson: Use consistent style for testsDylan Baker2018-01-111-4/+8
| | | | | | | Don't use intermediate variables, use consistent whitespace. Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* meson: Use consistent styleDylan Baker2018-01-111-4/+1
| | | | | | | | | | | | | | | | | | | | Currently the meosn build has a mix of two styles: arg : [foo, ... bar], and arg : [ foo, ..., bar, ] For consistency let's pick one. I've picked the later style, which I think is more readable, and is more common in the mesa code base. v2: - fix commit message Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* broadcom/vc5: Fix discard_if during control flow.Eric Anholt2018-01-031-1/+1
| | | | | | | I want to do the SETMSF.IFA to discard only if execute == 0 and cond, so our dest of the PUSHZ needs to be nonzero if execute or !cond are nonzero. Fixes dEQP-GLES3.functional.shaders.discard.dynamic_loop_dynamic.
* broadcom/vc5: Don't emit component 3/4 F16 TLB writes for float/vec2.Eric Anholt2018-01-031-1/+2
| | | | | Fixes a simulator assertion failure on dEQP-GLES3.functional.fragment_out.array.fixed.r8_highp_float.
* broadcom/vc5: Introduce enums for internal depth/type, with V3D prefixes.Eric Anholt2018-01-031-27/+28
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* broadcom/xml: Fix up safe name confusion with prefixing.Eric Anholt2018-01-031-14/+13
| | | | | | | For enums we were doubling the underscore if the value had a numeric first character of its name (which safe_name() adds an underscore to). A little helper function cleans up the other instance of prefixing while also fixing this.
* broadcom/vc5: Turn the decimate mode field into an enum in the XML.Eric Anholt2018-01-031-1/+8
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* broadcom/vc5: Turn the output image format into an enum.Eric Anholt2018-01-031-51/+55
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* broadcom/vc5: Turn the CLE XML's memory format into an enum.Eric Anholt2018-01-031-16/+11
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* broadcom/vc5: Emit flat shade flags for varying components > 24.Eric Anholt2018-01-033-7/+20
| | | | | | | | | | This means that with no flatshading we'll emit the single-byte ZERO_ALL_FLAT_SHADE_FLAGS, and otherwise emit a set of FLAT_SHADE_FLAGS to get all the bits we need set. There's a _SET enum in the packet we could use to possibly set entire ranges of the bitfield without using another packet, but this at least fixes the conformance failure.
* broadcom/vc5: Emit proper flatshading code for glShadeModel(GL_FLAT).Eric Anholt2018-01-033-20/+14
| | | | | | | | In updating the simulator, behavior changed slightly so that our old code wasn't getting glxgears's flatshading interpolated right. Emit flat shading code just like we would for a normal flat-shaded varying, by passing a flag in the shader key for glShadeModel(GL_FLAT) state and customizing the color inputs based on that.
* braodcom/vc5: Rely on OVRTMUOUT always being set.Eric Anholt2018-01-031-0/+2
| | | | | | | | | | | | | | It seems that the HW team has decided that it's the only supported mode, and it's the mode I actually meant to be using but forgot. Our table of return_32_bit should have matched the default non-OVRTMUOUT behavior, so this change should be invisible. However, the change revealed that some my return_size checks for swizzling were a bit confused in the shadow case, so I had to move them to draw time once we have both the sampler and the view together. Fixes assertion failures in the updated simulator, where the non-OVRTMUOUT support has been removed.
* broadcom/vc5: Move texture return channel setup into the compiler.Eric Anholt2018-01-033-18/+41
| | | | | | | | The compiler decides how many LDTMUs we're going to emit, and that must match the P1 flags. This brings the return channel counting to a single place (so all that's passed into the compiler is "how many return channels you may request from this texture's format), and was a necessary step for shadow samplers once we stop using OVRTMUOUT=0.
* broadcom/vc5: Add missing setting of the UIF XOR disable flag in textures.Eric Anholt2017-12-191-0/+1
| | | | | Most piglit textures happened to work out by RGBW not changing in that bit, but it did cause failures in RGBA16F fbo-generatemipmap-formats.
* broadcom/vc5: Fix a typo in memcmp for sig unpack checking.Eric Anholt2017-12-141-1/+1
| | | | | | | This shockingly ended up working out, because only the first byte of *sig is used and (sizeof(*sig) != 0) == 1. Fixes a compiler warning. Link: https://bugs.freedesktop.org/show_bug.cgi?id=104183
* broadcom/vc5: Enable NIR txd lowering on all txd instructions.Eric Anholt2017-12-141-0/+1
| | | | | | | | Fixes almost all of piglit's arb_shader_texture_lod grad tests, except for the base -texgrad/texgradcube ones which fail on what appear to be precision problems. Reviewed-by: Ian Romanick <[email protected]>
* broadcom/vc5: Fix shader input/outputs for gallium's new NIR linking.Eric Anholt2017-12-141-4/+8
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* meson: add dep_thread to every lib that includes threads.hEric Engestrom2017-12-071-1/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104141 Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* broadcom/vc4: Use the new enum functionality of the XML to decode better.Eric Anholt2017-12-011-20/+25
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* broadcom: use NDEBUG to guard assertsEric Engestrom2017-11-281-5/+5
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* broadcom/vc5: Fix BASE_LEVEL handling with txl.Eric Anholt2017-11-221-2/+4
| | | | | | | The HW doesn't add the base level anywhere (the min/max lod clamping is what does base level), so we need to add it manually in this case. Fixes piglit tex-miplevel-selection *Lod 2D.
* broadcom/vc5: Fix up integer texture handling.Eric Anholt2017-11-191-0/+23
| | | | | | | | The original spec I had didn't expose integer textures and suggested that you use unfiltered floats. Now there are proper formats for them. Fixes 16- and 32-bit texwrap integer tests in piglit, and dEQP-GLES3.functional.fbo.completeness.renderable.renderbuffer.color0.rgb10_a2ui.
* broadcom/vc5: Ensure that there is always a TLB write.Eric Anholt2017-11-171-1/+17
| | | | | This should fix some GPU hangs in our (currently always single-threaded) fragment shaders, and definitely fixes assertion failures in simulation.
* broadcom/vc5: Remove unused v3d_compiler.cAndreas Boll2017-11-081-43/+0
| | | | | | | | | | | Unused since original import of VC5. Fixes: ade416d0236 ("broadcom: Add VC5 NIR compiler.") Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* broadcom/vc5: Do 16-bit unpacking of integer texture returns properly.Eric Anholt2017-11-071-8/+29
| | | | | We were doing f16 unpacks, which trashed "1" values. Fixes many piglit texwrap GL_EXT_texture_integer cases.
* broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.Eric Anholt2017-11-072-5/+33
| | | | | | | The v3d_qpu_writes_r*() were only checking for fixed-function accumulator writes, not normal ALU writes to those regs. Fixes fs-discard-exit-2 on simulation (but not HW).
* broadcom/vc5: Add occlusion query support.Eric Anholt2017-11-071-0/+4
| | | | Fixes all of piglit's OQ tests.
* broadcom/vc5: Fix mipmap filtering enums.Eric Anholt2017-11-071-2/+24
| | | | | | | | The ordering of the values was even less obvious than I thought, with both the mip filter and the min filter being in different bits depending on whether the mip filter is none. Fixes piglit fs-textureLod-miplevels.shader_test
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