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This instruction is used to ensure that TMU stores have been processed
before moving on. In particular, you need any TMU ops to be done by the
time the shader ends.
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Reported-by: Rob Clark <[email protected]>
Fixes: e92959c4e03c ("v3d: Pass the whole clif_dump structure to v3d_print_group().")
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These instructions let us write directly to the phys regfile, instead of
just R4. That lets us avoid moving out of R4 to avoid conflicting with
other SFU results, and to avoid conflicting with thread switches.
There is still an extra instruction of latency, which is not represented
in the scheduler at the moment. If you use the result before it's ready,
the QPU will just stall, unlike the magic R4 mode where you'd read the
previous value. That means that the following shader-db results aren't
quite representative (since we now cause some stalls instead of emitting
nops), but they're impressive enough that I'm happy with the change.
total instructions in shared programs: 95669 -> 91275 (-4.59%)
instructions in affected programs: 82590 -> 78196 (-5.32%)
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These instructions allow writing the result to any register, instead of a
special writeback to r4.
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Noticed while trying to sort a new op into the appropriate place to match
the documentation.
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If we fail initial disassembly, it's good to know what instruction it was
that failed.
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This will be used for detecting last thread segment in register spilling.
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These helpers will be used in register spilling to determine where to add
a last thrsw if needed, and might help refactor QPU scheduling.
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The QPU scheduling code calling this function already separately checked
this signal.
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This will be reused in register spilling.
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After the 4.1 spec, 4.2 retroactively renamed patchid to barrierid because
it's used for other barriers in compute.
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The V3D 3.x series of TMU writes with meaning depending on the texture
type is replaced with writes to specific registers for each texture
argument semantic.
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I had a .ifb being decoded weird in sampid, so this is to check that .ifb
is fine.
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Now, instead of a magic write register for VPM stores we have an
instruction to do them (which means no packing of other ALU ops into it),
with the ability to reorder the VPM stores due to the offset being baked
into the instruction.
VPM loads also gain the ability to be reordered by packing the row into
the A argument. They also no longer write to the r3 accumulator, and
instead must be stored to a physical register.
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I had all the packing code in this file at one point, but these defines
now live in qpu_pack.c.
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Signals are more complicated than that, and tables ended up being better.
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The WRTMUC replaces the implicit uniform loads in the first two texture
instructions. LDVPM disappears in favor of an ALU op. LDVARY, LDTMU,
LDTLB, and LDUNIF*RF now write to arbitrary registers, which required
passing the devinfo through to a few more functions.
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Don't use intermediate variables, use consistent whitespace.
Acked-by: Eric Engestrom <[email protected]>
Signed-off-by: Dylan Baker <[email protected]>
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This shockingly ended up working out, because only the first byte of *sig
is used and (sizeof(*sig) != 0) == 1. Fixes a compiler warning.
Link: https://bugs.freedesktop.org/show_bug.cgi?id=104183
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The v3d_qpu_writes_r*() were only checking for fixed-function accumulator
writes, not normal ALU writes to those regs.
Fixes fs-discard-exit-2 on simulation (but not HW).
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I typoed and was depending on v3d_xml.h (the gzipped xml)_, not on the
v3d_packet_v33_pack.h that the compiler and QPU packing actually use.
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v2: Default vc5 to off, since it requires the simulator currently. Add
missing dep on the XML generation from libbroadcom_vc5.
Reviewed-by: Dylan Baker <[email protected]> (v1)
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Unlike VC4, I've defined an unpacked instruction format with pack/unpack
functions to convert to 64-bit encoded instructions. This will let us
incrementally put together our instructions and validate them in a more
natural way than the QPU_GET_FIELD/QPU_SET_FIELD used to.
The pack/unpack unfortuantely are written by hand. While I could define
genxml for parts of it, there are many special cases (like operand order
of commutative binops choosing which binop is being performed!) and it
probably wouldn't come out much cleaner.
The disasm unit test ensures that we have the same assembly format as
Broadcom's internal tools, other than whitespace changes.
v2: Fix automake variable redefinition complaints, add test to .gitignore
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