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* broadcom/vc5: Add a test for .ifb in ADD ops.Eric Anholt2018-01-121-0/+1
| | | | | I had a .ifb being decoded weird in sampid, so this is to check that .ifb is fine.
* broadcom/vc5: Add the new tesselation opcodes in V3D 4.1.Eric Anholt2018-01-122-1/+5
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* broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.Eric Anholt2018-01-124-12/+110
| | | | | | | | | | | Now, instead of a magic write register for VPM stores we have an instruction to do them (which means no packing of other ALU ops into it), with the ability to reorder the VPM stores due to the offset being baked into the instruction. VPM loads also gain the ability to be reordered by packing the row into the A argument. They also no longer write to the r3 accumulator, and instead must be stored to a physical register.
* broadcom/vc5: Drop dead VC5_QPU_* defines from qpu_instr.c.Eric Anholt2018-01-121-80/+0
| | | | | I had all the packing code in this file at one point, but these defines now live in qpu_pack.c.
* broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates.Eric Anholt2018-01-124-1/+94
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* broadcom/vc5: Drop signal bit #defines.Eric Anholt2018-01-122-8/+0
| | | | Signals are more complicated than that, and tables ended up being better.
* broadcom/vc5: Add support for V3Dv4 signal bits.Eric Anholt2018-01-125-24/+220
| | | | | | | The WRTMUC replaces the implicit uniform loads in the first two texture instructions. LDVPM disappears in favor of an ALU op. LDVARY, LDTMU, LDTLB, and LDUNIF*RF now write to arbitrary registers, which required passing the devinfo through to a few more functions.
* broadcom/vc5: Fix pack/unpack of vfmul input unpack flags.Eric Anholt2018-01-122-0/+40
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* meson: Use consistent style for testsDylan Baker2018-01-111-4/+8
| | | | | | | Don't use intermediate variables, use consistent whitespace. Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* broadcom/vc5: Fix a typo in memcmp for sig unpack checking.Eric Anholt2017-12-141-1/+1
| | | | | | | This shockingly ended up working out, because only the first byte of *sig is used and (sizeof(*sig) != 0) == 1. Fixes a compiler warning. Link: https://bugs.freedesktop.org/show_bug.cgi?id=104183
* broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.Eric Anholt2017-11-071-2/+28
| | | | | | | The v3d_qpu_writes_r*() were only checking for fixed-function accumulator writes, not normal ALU writes to those regs. Fixes fs-discard-exit-2 on simulation (but not HW).
* meson: Fix vc5 deps on the XML-generated headers.Eric Anholt2017-10-201-1/+1
| | | | | I typoed and was depending on v3d_xml.h (the gzipped xml)_, not on the v3d_packet_v33_pack.h that the compiler and QPU packing actually use.
* meson: Add support for the vc5 driver.Eric Anholt2017-10-171-0/+39
| | | | | | | v2: Default vc5 to off, since it requires the simulator currently. Add missing dep on the XML generation from libbroadcom_vc5. Reviewed-by: Dylan Baker <[email protected]> (v1)
* broadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm.Eric Anholt2017-10-108-0/+2746
Unlike VC4, I've defined an unpacked instruction format with pack/unpack functions to convert to 64-bit encoded instructions. This will let us incrementally put together our instructions and validate them in a more natural way than the QPU_GET_FIELD/QPU_SET_FIELD used to. The pack/unpack unfortuantely are written by hand. While I could define genxml for parts of it, there are many special cases (like operand order of commutative binops choosing which binop is being performed!) and it probably wouldn't come out much cleaner. The disasm unit test ensures that we have the same assembly format as Broadcom's internal tools, other than whitespace changes. v2: Fix automake variable redefinition complaints, add test to .gitignore
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